PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 215
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6527-I/PT
Manufacturer Part Number
PIC18F6527-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(446 pages)
3.PIC18F8627T-IPT.pdf
(44 pages)
4.PIC18F6527-IPT.pdf
(10 pages)
5.PIC18F8622-IPT.pdf
(448 pages)
Specifications of PIC18F6527-I/PT
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6527-I/PT
Manufacturer:
NOVACAP
Quantity:
20 000
Company:
Part Number:
PIC18F6527-I/PT
Manufacturer:
Microchi
Quantity:
1 760
Company:
Part Number:
PIC18F6527-I/PT
Manufacturer:
MICROCHIP
Quantity:
8
Company:
Part Number:
PIC18F6527-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6527-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- PIC18F8627T-IPT PDF datasheet #3
- PIC18F6527-IPT PDF datasheet #4
- PIC18F8622-IPT PDF datasheet #5
- Current page: 215 of 446
- Download datasheet (7Mb)
19.3.8
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In Idle modes, a clock is provided to the peripherals.
That clock can be from the primary clock source, the
secondary clock (Timer1 oscillator) or the INTOSC
source. See Section 2.7 “Clock Sources and
Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Trans-
mit/Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
19.3.9
A Reset disables the MSSP module and terminates the
current transfer.
© 2008 Microchip Technology Inc.
OPERATION IN POWER-MANAGED
MODES
EFFECTS OF A RESET
19.3.10
Table 19-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 19-1:
There is also an SMP bit which controls when the data
is sampled.
19.3.11
Because MSSP1 and MSSP2 are independent
modules, they can operate simultaneously at different
data rates. Setting the SSPM3:SSPM0 bits of the
SSPxCON register determines the rate for the
corresponding module.
An exception is when both modules use Timer2 as a
time base in Master mode. In this instance, any
changes to the Timer2 module’s operation will affect
both MSSP modules equally. If different bit rates are
required for each module, the user should select one of
the other three time base options for one of the
modules.
PIC18F8722 FAMILY
Standard SPI Mode
Terminology
0, 0
0, 1
1, 0
1, 1
BUS MODE COMPATIBILITY
SPI CLOCK SPEED AND MODULE
INTERACTIONS
SPI BUS MODES
CKP
Control Bits State
0
0
1
1
DS39646C-page 213
CKE
1
0
1
0
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