PIC18F442-I/L Microchip Technology, PIC18F442-I/L Datasheet - Page 153

• Manufacturer Part Number: PIC18F442-I/L
• Description: IC MCU FLASH 8KX16 EE A/D 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F442-I/L

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: MSSP, SPI, I2C, PSP, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Package: 44PLCC
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCCXLT44L2 - SOCKET TRAN ICE 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCCDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F442I/L

15.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 15-17). When a write occurs
to SSPBUF, the baud rate generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 15-17:
TABLE 15-3:
© 2006 Microchip Technology Inc.
Note 1: The I
2
C Master mode, the baud rate generator (BRG)
2: Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
BAUD RATE GENERATOR
100 kHz) in all details, but may be used with care where higher rates are required by the application.
low time of clock period, producing the effective frequency.
F
CY
2
I
2
C interface does not conform to the 400 kHz I
C CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
2
C Master mode, the BRG is
SCL
SSPM3:SSPM0
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
F
CY
CY
*2
) on the
Control
Reload
CLKO
Reload
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
BRG Down Counter
2
C specification (which applies to rates greater than
SSPADD<6:0>
BRG Value
0Dh
3Fh
0Ah
0Ah
19h
20h
28h
03h
00h
PIC18FXX2
Fosc/4
(2 Rollovers of BRG)
400 kHz
400 kHz
333 kHz
312.5 kHz
DS39564C-page 151
1 MHz
100 kHz
308 kHz
100 kHz
100kHz
F
SCL (2)
(1)
(1)
(1)
(1)