PIC16LC73A-04/SO Microchip Technology, PIC16LC73A-04/SO Datasheet - Page 69

• Manufacturer Part Number: PIC16LC73A-04/SO
• Description: IC MCU OTP 4KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC73A-04/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.0
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
reset.
The input clock (F
1:4
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 9-2 shows the Timer2 control register.
1997 Microchip Technology Inc.
or
TIMER2 MODULE
Applicable Devices
72 73 73A 74 74A 76 77
1:16,
OSC
selected
/4) has a prescale option of 1:1,
by
control
bits
9.1
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
TMR2 is not cleared when T2CON is written.
9.2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 9-1:
Note 1: TMR2 register output can be software selected
Watchdog Timer reset, or Brown-out Reset)
Sets flag
bit TMR2IF
1:1
Postscaler
Timer2 Prescaler and Postscaler
Output of TMR2
to
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
by the SSP Module as a baud clock.
1:16
4
TMR2
output
Reset
EQ
TIMER2 BLOCK DIAGRAM
(1)
Comparator
TMR2 reg
PR2 reg
PIC16C7X
1:1, 1:4, 1:16
Prescaler
DS30390E-page 69
2
F
OSC
/4