PIC18LF248-I/SO Microchip Technology, PIC18LF248-I/SO Datasheet - Page 165

• Manufacturer Part Number: PIC18LF248-I/SO
• Description: IC MCU CAN FLASH 8K 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF248-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.4.5
If a user clears the CKP bit, the SCL output is forced to
‘0’. Setting the CKP bit will not assert the SCL output
low until the SCL output is already sampled low. If the
user attempts to drive SCL low, the CKP bit will not
FIGURE 17-12:
© 2006 Microchip Technology Inc.
WR
SSPCON1
SDA
SCL
CKP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Clock Synchronization and
the CKP bit
CLOCK SYNCHRONIZATION TIMING
Master device
asserts clock
DX
assert the SCL line until an external I
has already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other devices
on the I
a write to the CKP bit will not violate the minimum high
time requirement for SCL (see Figure 17-12).
Master device
deasserts clock
2
C bus have deasserted SCL. This ensures that
PIC18FXX8
DS41159E-page 163
2
DX – 1
C master device