PIC18LF248-I/SO Microchip Technology, PIC18LF248-I/SO Datasheet - Page 62

• Manufacturer Part Number: PIC18LF248-I/SO
• Description: IC MCU CAN FLASH 8K 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF248-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 5-1:
DS41159E-page 60
PIC18FXX8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EECON1: EEPROM CONTROL REGISTER 1
bit 7
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access Configuration registers
0 = Access program Flash or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write only
WRERR: Write Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM or Flash memory
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
0 = Write cycle is complete
RD: Read Control bit
1 = Initiates an EEPROM read
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
-n = Value at POR
EEPGD
R/W-x
Note:
(reset by hardware)
(any MCLR or any WDT Reset during self-timed programming in normal operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
R/W-x
CFGS
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
S = Settable bit
‘0’ = Bit is cleared
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
WREN
R/W-0
© 2006 Microchip Technology Inc.
R/S-0
WR
R/S-0
RD
bit 0