PIC16C76-20I/SP Microchip Technology, PIC16C76-20I/SP Datasheet - Page 14
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PIC16C76-20I/SP
Manufacturer Part Number
PIC16C76-20I/SP
Description
IC MCU OTP 8KX14 A/D PWM 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C72-04SO.pdf
(289 pages)
5.PIC16C76-04SP.pdf
(8 pages)
Specifications of PIC16C76-20I/SP
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
OTP
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
368Byte
Cpu Speed
10MHz
No. Of Timers
3
Interface
I2C, SPI, USART
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Package
28SPDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
22
Interface Type
I2C/SPI/USART
On-chip Adc
5-chx8-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC16C63A/65B/73B/74B
3.1
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
FIGURE 3-2:
EXAMPLE 3-1:
DS30605C-page 14
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
5. Instruction @ address SUB_1
Note:
OSC2/CLKOUT
Clocking Scheme/Instruction
Cycle
(RC mode)
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is
“flushed” from the pipeline, while the new instruction is being fetched and then executed.
SUB_1
PORTA, BIT3 (Forced NOP)
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
T
PC
CY
0
Q3
Q4
Execute 1
Fetch 2
T
CY
1
Q1
Execute INST (PC)
Fetch INST (PC+1)
Execute 2
Q2
Fetch 3
T
PC+1
CY
2
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
T
CY
3
Q1
Execute INST (PC+1)
Fetch INST (PC+2)
Fetch SUB_1 Execute SUB_1
Q2
Flush
T
PC+2
CY
2000 Microchip Technology Inc.
4
Q3
Q4
T
CY
Internal
phase
clock
5