PIC18F4680-I/P Microchip Technology, PIC18F4680-I/P Datasheet - Page 257
PIC18F4680-I/P
Manufacturer Part Number
PIC18F4680-I/P
Description
IC MCU FLASH 32KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4585-IPT.pdf
(482 pages)
4.PIC18F4585-IPT.pdf
(14 pages)
5.PIC18F4585-IPT.pdf
(8 pages)
6.PIC18F4585-IPT.pdf
(12 pages)
7.PIC18F4585-IPT.pdf
(4 pages)
8.PIC18F2680-ISO.pdf
(484 pages)
Specifications of PIC18F4680-I/P
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SPI/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
44
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 25 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4680 - BOARD DAUGHTER ICEPIC3DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4680-I/PT
Manufacturer:
LATTICE
Quantity:
2 667
Company:
Part Number:
PIC18F4680-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4585-IPT PDF datasheet #3
- PIC18F4585-IPT PDF datasheet #4
- PIC18F4585-IPT PDF datasheet #5
- PIC18F4585-IPT PDF datasheet #6
- PIC18F4585-IPT PDF datasheet #7
- PIC18F2680-ISO PDF datasheet #8
- Current page: 257 of 484
- Download datasheet (10Mb)
19.6
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 T
time before the conversion starts.
FIGURE 19-3:
FIGURE 19-4:
2004 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO bit
T
CY
Set GO bit
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
1
- T
T
AD
ACQT
Conversion starts
Acquisition
Automatic
2
T
Time
AD
Cycles
1 T
A/D CONVERSION T
A/D CONVERSION T
3
AD
b9
2 T
4
AD
b8
Conversion starts
(Holding capacitor is disconnected)
3 T
1
AD
b7
AD
4 T
b9
2
acquisition
AD
PIC18F2585/2680/4585/4680
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
b8
3
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
Preliminary
AD
b5
6 T
b7
4
AD
b4
7 T
T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
5
b6
AD
AD
b3
Note:
AD
Cycles
8
b5
wait is required before the next acquisition can
6
conversion
T
AD
b2
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
b4
7
AD
b1
10
b3
T
8
AD
sample.
b0
ACQ
11
ACQ
b2
9
= 0)
= 4 T
10
This
b1
AD
DS39625B-page 255
)
b0
11
means
the
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