DSPIC30F5013-30I/PT Microchip Technology, DSPIC30F5013-30I/PT Datasheet - Page 98
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DSPIC30F5013-30I/PT
Manufacturer Part Number
DSPIC30F5013-30I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F5011-20IPT.pdf
(220 pages)
2.DSPIC30F5011-20IPT.pdf
(16 pages)
3.DSPIC30F5011-20IPT.pdf
(6 pages)
4.DSPIC30F5011-20IPT.pdf
(14 pages)
5.DSPIC30F5011-20IPT.pdf
(26 pages)
6.DSPIC30F5011-20IPTG.pdf
(222 pages)
Specifications of DSPIC30F5013-30I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
66KB
Supply Voltage Range
2.5V To 5.5V
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
68
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPDM300004-2 - BOARD DEMO DSPICDEM.NET 2DM300004-1 - BOARD DEMO DSPICDEM.NET 1AC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F501330IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5013-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F5011/5013
15.12.3
In I
located in the I2CBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock arbi-
tration is taking place, for instance, the BRG is reloaded
when the SCL pin is sampled high.
As per the I
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 15-1:
15.12.4
Clock arbitration occurs when the master deasserts the
SCL pin (SCL allowed to float high) during any receive,
transmit, or Restart/Stop condition. When the SCL pin
is allowed to float high, the Baud Rate Generator is
suspended from counting until the SCL pin is actually
sampled high. When the SCL pin is sampled high, the
Baud Rate Generator is reloaded with the contents of
I2CBRG and begins counting. This ensures that the
SCL high time will always be at least one BRG rollover
count in the event that the clock is held low by an
external device.
15.12.5
Multi-master operation support is achieved by bus arbi-
tration. When the master outputs address/data bits
onto the SDA pin, arbitration takes place when the
master outputs a ‘1’ on SDA by letting SDA float high
while another master asserts a ‘0’. When the SCL pin
floats high, data should be stable. If the expected data
on SDA is a ‘1’ and the data sampled on the SDA
pin = 0, then a bus collision has taken place. The
master will set the MI2CIF pulse and Reset the master
portion of the I
DS70116H-page 98
2
C Master mode, the reload value for the BRG is
I2CBRG =
BAUD RATE GENERATOR
CLOCK ARBITRATION
MULTI-MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
2
C standard, F
2
C port to its Idle state.
(
F
F
SCK
SERIAL CLOCK RATE
CY
–
SCK
1,111,111
may be 100 kHz or
F
CY
)
– 1
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the TBF flag is
cleared, the SDA and SCL lines are de-asserted and a
value can now be written to I2CTRN. When the user
services the I
tine, if the I
can resume communication by asserting a Start
condition.
If a Start, Restart, Stop or Acknowledge condition was
in progress when the bus collision occurred, the condi-
tion is aborted, the SDA and SCL lines are de-asserted
and the respective control bits in the I2CCON register
are cleared to ‘0’. When the user services the bus col-
lision Interrupt Service Routine, and if the I
free, the user can resume communication by asserting
a Start condition.
The master will continue to monitor the SDA and SCL
pins, and if a Stop condition occurs, the MI2CIF bit will
be set.
A write to the I2CTRN will start the transmission of data
at the first data bit regardless of where the transmitter
left off when bus collision occurred.
In a multi-master environment, the interrupt generation
on the detection of Start and Stop conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the I2CSTAT
register, or the bus is Idle and the S and P bits are
cleared.
15.13 I
15.13.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’. If
Sleep occurs in the middle of a transmission and the
state machine is partially into a transmission as the
clocks stop, then the transmission is aborted. Similarly,
if Sleep occurs in the middle of a reception, then the
reception is aborted.
15.13.2
For the I
stop on Idle or continue on Idle. If I2CSIDL = 0, the
module will continue operation on assertion of the Idle
mode. If I2CSIDL = 1, the module will stop on Idle.
2
Sleep and Idle Modes
2
C, the I2CSIDL bit selects if the module will
2
C Module Operation During CPU
I
SLEEP MODE
I
MODE
C bus is free (i.e., the P bit is set), the user
2
2
C OPERATION DURING CPU
C OPERATION DURING CPU IDLE
2
C master event Interrupt Service Rou-
© 2008 Microchip Technology Inc.
2
C bus is
2
C