AT32UC3B1256-Z1UT Atmel, AT32UC3B1256-Z1UT Datasheet - Page 65

• Manufacturer Part Number: AT32UC3B1256-Z1UT
• Description: IC MCU AVR32 256KB FLASH 48-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-Z1UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32059K–03/2011
- USB
- ADC
- PDCA
- TWI
1.
1. Sleep Mode activation needs addtionnal A to D conversion
1. Wrong PDCA behavior when using two PDCA channels with the same PID
2. Transfer error will stall a transmit peripheral handshake interface
1. The TWI RXRDY flag in SR register is not reset when a software reset is performed
2. TWI in master mode will continue to read data
3. TWI slave behaves improperly if master acknowledges the last transmitted data byte
As a consequence, isochronous IN and OUT tokens are sent every 1 ms (Full Speed), or
every 125 uS (High Speed).
Fix/Workaround
ForHigher polling time, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
Wrong PDCA behavior when using two PDCA channels with the same PID.
Fix/Workaround
The same PID should not be assigned to more than one channel.
If a tranfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
The TWI RXRDY flag in SR register is not reset when a software reset is performed.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
TWI in master mode will continue to read data on the line even if the shift register and the
RHR register are full. This will generate an overrun error.
Fix/Workaround
To prevent this, read the RHR register as soon as a new RX data is ready.
before a STOP condition
In I2C slave transmitter mode, if the master acknowledges the last data byte before a STOP
condition (what the master is not supposed to do), the following TWI slave receiver mode
frame may contain an inappropriate clock stretch. This clock stretch can only be stopped by
resetting the TWI.
Fix/Workaround
If the TWI is used as a slave transmitter with a master that acknowledges the last data byte
before a STOP condition, it is necessary to reset the TWI beforeentering slave receiver
mode.
UPCFGn.INTFRQ is irrelevant for isochronous pipe
AT32UC3B
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