AT32UC3B1256-Z1UT Atmel, AT32UC3B1256-Z1UT Datasheet - Page 99

• Manufacturer Part Number: AT32UC3B1256-Z1UT
• Description: IC MCU AVR32 256KB FLASH 48-QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-Z1UT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32059K–03/2011
- Processor and Architecture
1. Local Busto fast GPIO not available on silicon Rev B
2. Memory Protection Unit (MPU) is non functional
3. Bus error should be masked in Debug mode
4. Read Modify Write (RMW) instructions on data outside the internal RAM does not
5. Need two NOPs instruction after instructions masking interrupts
6. Clock connection table on Rev B
Figure 12-1. Timer/Counter clock connections on RevB
7. Spurious interrupt may corrupt core SR mode to exception
Source
Internal
External
Local bus is only available for silicon RevE and later.
Fix/Workaround
Memory Protection Unit (MPU) is non functional.
Fix/Workaround
Do not use the MPU.
If a bus error occurs during debug mode, the processor will not respond to debug com-
mands through the DINST register.
Fix/Workaround
A reset of the device will make the CPU respond to debug commands again.
work
Read Modify Write (RMW) instructions on data outside the internal RAM does not work.
Fix/Workaround
Do not perform RMW instructions on data outside the internal RAM.
The instructions following in the pipeline the instruction masking the interrupt through SR
may behave abnormally.
Fix/Workaround
Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR
Here is the table of Rev B
If the rules listed in the chapter `Masking interrupt requests in peripheral modules' of the
AVR32UC Technical Reference Manual are not followed, a spurious interrupt may occur. An
Do not use if silicon revison older than F.
Name
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
Connection
32KHz Oscillator
PBA Clock / 4
PBA Clock / 8
PBA Clock / 16
PBA Clock / 32
AT32UC3B
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