PIC18F6585-I/PT Microchip Technology, PIC18F6585-I/PT Datasheet - Page 390

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: IC PIC MCU FLASH 24KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6585-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS30491C-page 388
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
0x9A
0xBF
Inclusive OR literal with W
[ label ]
0
(W) .OR. k
N, Z
The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
1
1
literal ‘k’
IORLW
Read
0000
Q2
k
255
IORLW k
1001
0x35
Process
W
Data
Q3
kkkk
Write to W
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
RESULT =
W
RESULT =
W
Q1
=
=
register ‘f’
Inclusive OR W with f
[ label ]
0
d
a
(W) .OR. (f)
N, Z
Inclusive OR W with register ‘f’. If
‘d’ is ‘0’, the result is placed in W. If
‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
1
1
IORWF
Read
0001
Q2
0x13
0x91
0x13
0x93
f
[0,1]
[0,1]
 2004 Microchip Technology Inc.
255
RESULT, 0, 1
IORWF
00da
Process
Data
Q3
dest
ffff
f [,d [,a]]
destination
Write to
Q4
ffff