PIC18F6621-I/PT Microchip Technology, PIC18F6621-I/PT Datasheet - Page 295
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6621-I/PT
Manufacturer Part Number
PIC18F6621-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F6621-I/PT
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC18
No. Of I/o's
53
Eeprom Memory Size
1024Byte
Ram Memory Size
3.75KB
Cpu Speed
40MHz
No. Of Timers
5
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6621-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F6621-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6525-IPT PDF datasheet #2
- PIC18F6525-IPT PDF datasheet #3
- PIC18F6525-IPT PDF datasheet #4
- Current page: 295 of 396
- Download datasheet (8Mb)
CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2005 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
W
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
=
=
>
=
≤
=
register ‘f’
operation
operation
operation
Compare f with W, Skip if f > W
[ label ] CPFSGT
0 ≤ f ≤ 255
a ∈ [0,1]
(f) − (W);
skip if (f) > (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note:
HERE
NGREATER
GREATER
Read
0110
No
No
No
Q2
Q2
Q2
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
3 cycles if skip and followed
by a 2-word instruction.
010a
operation
operation
operation
CPFSGT REG, 0
:
:
Process
Data
No
No
No
Q3
Q3
Q3
f [,a]
ffff
operation
operation
operation
operation
PIC18F6525/6621/8525/8621
No
No
No
No
Q4
Q4
Q4
ffff
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
W
If REG
If REG
Q1
Q1
Q1
PC
PC
=
=
<
=
≥
=
register ‘f’
operation
operation
operation
Compare f with W, Skip if f < W
[ label ] CPFSLT
0 ≤ f ≤ 255
a ∈ [0,1]
(f) – (W);
skip if (f) < (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’ is ‘1’,
the BSR will not be overridden (default).
1
1(2)
Note:
HERE
NLESS
LESS
Read
0110
No
No
No
Q2
Q2
Q2
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
3 cycles if skip and followed
by a 2-word instruction.
CPFSLT REG, 1
:
:
000a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS39612B-page 293
f [,a]
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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