PIC16C74A-20I/L Microchip Technology, PIC16C74A-20I/L Datasheet - Page 89

• Manufacturer Part Number: PIC16C74A-20I/L
• Description: IC MCU OTP 4KX14 A/D PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74A-20I/L

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 192 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

11.4
This section provides an overview of the Inter-Inte-
grated Circuit (I
the operation of the SSP module in I
The I
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. The enhanced specification (fast mode) is also
supported. This device will communicate with both
standard and fast mode devices if attached to the same
bus. The clock will determine the data rate.
The I
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard-
ware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXX software. Table 11-3 defines some of the
I
I
ment “ The I
which can be obtained from the Philips Corporation.
In the I
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is they can be thought of as operating in either
of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
TABLE 11-3:
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization
2
2
C bus terminology. For additional information on the
C interface specification, refer to the Philips docu-
1997 Microchip Technology Inc.
2
2
C interface employs a comprehensive protocol to
C bus is a two-wire serial interface developed by
Term
2
I
C interface protocol each device has an
2
C™ Overview
2
C bus and how to use it.” #939839340011,
2
C) bus, with Section 11.5 discussing
I
2
C BUS TERMINOLOGY
The device which initiates the transfer, generates the clock and terminates the transfer.
The device addressed by a master.
same time without corrupting the message.
the transfer data does not get corrupted.
The device that sends the data to the bus.
The device that receives the data from the bus.
More than one master device in a system. These masters can attempt to control the bus at the
Procedure that ensures that only one of the master devices will control the bus. This ensure that
Procedure where the clock signals of two or more devices are synchronized.
2
C mode.
72 73 73A 74 74A 76 77
Applicable Devices
Description
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I
limited only by the maximum bus loading specification
of 400 pF.
11.4.1
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure 11-14 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data trans-
fer. Due to the definition of the START and STOP con-
ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
FIGURE 11-14: START AND STOP
SDA
SCL
Condition
Start
S
INITIATING AND TERMINATING DATA
TRANSFER
Change
Allowed
of Data
CONDITIONS
PIC16C7X
Change
Allowed
of Data
DS30390E-page 89
Condition
Stop
2
P
C bus is