DSPIC30F6013A-30I/PT Microchip Technology, DSPIC30F6013A-30I/PT Datasheet - Page 107
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DSPIC30F6013A-30I/PT
Manufacturer Part Number
DSPIC30F6013A-30I/PT
Description
IC DSPIC MCU/DSP 132K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F6011A-30IPT.pdf
(234 pages)
3.DSPIC30F6011A-30IPT.pdf
(8 pages)
4.DSPIC30F6011A-30IPT.pdf
(10 pages)
5.DSPIC30F6011A-30IPT.pdf
(6 pages)
6.DSPIC30F6011A-30IPT.pdf
(8 pages)
7.DSPIC30F6011A-30IPT.pdf
(16 pages)
8.DSPIC30F6014A-20EPT.pdf
(238 pages)
9.DSPIC30F6011A-30IPF.pdf
(236 pages)
Specifications of DSPIC30F6013A-30I/PT
Program Memory Type
FLASH
Program Memory Size
132KB (44K x 24)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
68
Data Ram Size
6 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300024, DM330011
Minimum Operating Temperature
- 40 C
Core Frequency
30MHz
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of I/o's
68
Flash Memory Size
132KB
Supply Voltage Range
2.5V To 5.5V
Operating Temperature Range
-40°C To
Rohs Compliant
Yes
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx12-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F6013A30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6013A-30I/PT
Manufacturer:
Microchip
Quantity:
1 096
Company:
Part Number:
DSPIC30F6013A-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
16.5.2
The FERR bit (UxSTA<2>) is set if a ‘0’ is detected
instead of a Stop bit. If two Stop bits are selected, both
Stop bits must be ‘1’, otherwise FERR will be set. The
read only FERR bit is buffered along with the received
data. It is cleared on any Reset.
16.5.3
The PERR bit (UxSTA<3>) is set if the parity of the
received word is incorrect. This error bit is applicable
only if a Parity mode (odd or even) is selected. The
read only PERR bit is buffered along with the received
data bytes. It is cleared on any Reset.
16.5.4
When the receiver is active (i.e., between the initial
detection of the Start bit and the completion of the Stop
bit), the RIDLE bit (UxSTA<4>) is ‘0’. Between the com-
pletion of the Stop bit and detection of the next Start bit,
the RIDLE bit is ‘1’, indicating that the UART is Idle.
16.5.5
The receiver will count and expect a certain number of
bit times based on the values programmed in the
PDSEL (UxMODE<2:1>) and STSEL (UxMODE<0>)
bits.
If the break is longer than 13 bit times, the reception is
considered complete after the number of bit times
specified by PDSEL and STSEL. The URXDA bit is set,
FERR is set, zeros are loaded into the receive FIFO,
interrupts are generated if appropriate and the RIDLE
bit is set.
When the module receives a long break signal and the
receiver has detected the Start bit, the data bits and the
invalid Stop bit (which sets the FERR), the receiver
must wait for a valid Stop bit before looking for the next
Start bit. It cannot assume that the break condition on
the line is the next Start bit.
Break is regarded as a character containing all ‘0’s with
the FERR bit set. The break character is loaded into the
buffer. No further reception can occur until a Stop bit is
received. Note that RIDLE goes high when the Stop bit
has not yet been received.
© 2011 Microchip Technology Inc.
FRAMING ERROR (FERR)
PARITY ERROR (PERR)
IDLE STATUS
RECEIVE BREAK
dsPIC30F6011A/6012A/6013A/6014A
16.6
Setting the ADDEN bit (UxSTA<5>) enables this spe-
cial mode in which a 9th bit (URX8) value of ‘1’ identi-
fies the received word as an address, rather than data.
This mode is only applicable for 9-bit data communica-
tion. The URXISEL control bit does not have any
impact on interrupt generation in this mode since an
interrupt (if enabled) will be generated every time the
received word has the 9th bit set.
16.7
Setting the LPBACK bit enables this special mode in
which the UxTX pin is internally connected to the UxRX
pin. When configured for the Loopback mode, the
UxRX pin is disconnected from the internal UART
receive logic. However, the UxTX pin still functions as
in a normal operation.
To select this mode:
1.
2.
3.
16.8
The UART has a 16-bit Baud Rate Generator to allow
maximum flexibility in baud rate generation. The Baud
Rate Generator register (UxBRG) is readable and
writable. The baud rate is computed as shown in
Equation
EQUATION 16-1:
Where:
BRG = 16-bit value held in UxBRG register
F
Therefore, the maximum baud rate possible is:
and the minimum baud rate possible is:
With a full 16-bit Baud Rate Generator at 30 MIPS
operation, the minimum baud rate achievable is
28.5 bps.
CY
Configure UART for desired mode of operation.
Set LPBACK = 1 to enable Loopback mode.
Enable transmission as defined in
“Transmitting
F
F
= Instruction Clock Rate (1/T
CY
CY
(0 through 65535)
/16 (if BRG = 0),
/(16 * 65536).
Address Detect Mode
Loopback Mode
Baud Rate Generator
16-1:
Baud Rate = F
Data”.
BAUD RATE
CY
/(16 * (BRG + 1))
CY
DS70143E-page 107
)
Section 16.3