PIC18F8722-I/PT Microchip Technology, PIC18F8722-I/PT Datasheet - Page 150
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F8722-I/PT
Manufacturer Part Number
PIC18F8722-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(6 pages)
3.DV164136.pdf
(446 pages)
4.PIC18F8627T-IPT.pdf
(44 pages)
5.PIC18LF6627-IPT.pdf
(16 pages)
6.PIC18F8622-IPT.pdf
(448 pages)
Specifications of PIC18F8722-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8722-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- PIC18F8627T-IPT PDF datasheet #4
- PIC18LF6627-IPT PDF datasheet #5
- PIC18F8622-IPT PDF datasheet #6
- Current page: 150 of 446
- Download datasheet (7Mb)
PIC18F8722 FAMILY
TABLE 11-9:
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
DS39646C-page 148
RE5/AD13/P1C
RE6/AD14/P1B
RE7/AD15/
ECCP2/P2A
Legend:
Note 1:
PORTE
LATE
TRISE
Name
Pin Name
2:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Implemented on 80-pin devices only.
TRISE7
LATE7
Bit 7
RE7
ECCP2
PORTE FUNCTIONS (CONTINUED)
Function
AD13
AD14
AD15
P2A
RE5
P1C
RE6
P1B
RE7
(1)
(2)
(2)
(2)
(1)
TRISE6
LATE6
Bit 6
RE6
Setting
TRIS
0
1
x
x
0
0
1
x
x
0
0
1
x
x
0
1
0
TRISE5
LATE5
Bit 5
RE5
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
TRISE4
LATE4
Bit 4
RE4
LATE<5> data output.
PORTE<5> data input.
External memory interface, address/data bit 13 output. Takes priority
over ECCP and port data.
External memory interface, data bit 13 input.
ECCP1 Enhanced PWM output, channel C. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<6> data output.
PORTE<6> data input.
External memory interface, address/data bit 14 output. Takes priority
over ECCP and port data.
External memory interface, data bit 14 input.
ECCP1 Enhanced PWM output, channel B. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
LATE<7> data output.
PORTE<7> data input.
External memory interface, address/data bit 15 output. Takes priority
over ECCP and port data.
External memory interface, data bit 15 input.
ECCP2 compare output and ECCP2 PWM output. Takes priority over
port data.
ECCP2 capture input.
ECCP2 Enhanced PWM output, channel A. Takes priority over port and
data. May be configured for tri-state during Enhanced PWM shutdown
events.
TRISE3
LATE3
Bit 3
RE3
TRISE2
LATE2
Bit 2
RE2
Description
TRISE1
LATE1
Bit 1
© 2008 Microchip Technology Inc.
RE1
TRISE0
LATE0
Bit 0
RE0
on page
Values
Reset
60
60
60
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