ATXMEGA256A3-AU Atmel, ATXMEGA256A3-AU Datasheet - Page 12
![MCU AVR 256K FLASH 1.8V 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATXMEGA256A3-AU
Manufacturer Part Number
ATXMEGA256A3-AU
Description
MCU AVR 256K FLASH 1.8V 64-TQFP
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheet
1.ATXMEGA64A3-MH.pdf
(134 pages)
Specifications of ATXMEGA256A3-AU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Package
64TQFP
Device Core
AVR
Family Name
XMEGA
Maximum Speed
32 MHz
Operating Supply Voltage
1.8|2.5|3.3 V
Data Bus Width
8|16 Bit
Number Of Programmable I/os
50
Interface Type
SPI/TWI/USART
On-chip Adc
2(8-chx12-bit)
On-chip Dac
2-chx12-bit
Number Of Timers
7
Processor Series
ATXMEGA256x
Core
AVR8
Data Ram Size
16 KB
Maximum Clock Frequency
32 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATXMEGA256A3-AUR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
7.4.1
7.4.2
7.4.3
8068T–AVR–12/10
I/O Memory
SRAM Data Memory
EEPROM Data Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the
eral Module Address Map” on page
The XMEGA A3 devices have internal SRAM memory for data storage.
The XMEGA A3 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
56.
XMEGA A3
”Periph-
12