ATMEGA128-16AU Atmel, ATMEGA128-16AU Datasheet

IC AVR MCU 128K 16MHZ 5V 64TQFP

ATMEGA128-16AU

Manufacturer Part Number
ATMEGA128-16AU
Description
IC AVR MCU 128K 16MHZ 5V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA128-16AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4096Byte
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Features
High-performance, Low-power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
– 128Kbytes of In-System Self-programmable Flash program memory
– 4Kbytes EEPROM
– 4Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64Kbytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
– 2.7 - 5.5V ATmega128L
– 4.5 - 5.5V ATmega128
– 0 - 8MHz ATmega128L
– 0 - 16MHz ATmega128
Capture Mode
Extended Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
AVR
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128KBytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Summary
Rev. 2467VS–AVR–02/11

Related parts for ATMEGA128-16AU

ATMEGA128-16AU Summary of contents

Page 1

... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V ATmega128L – 4.5 - 5.5V ATmega128 • Speed Grades – 8MHz ATmega128L – 16MHz ATmega128 ® ® AVR 8-bit Microcontroller (1) 8-bit Microcontroller with 128KBytes In-System ...

Page 2

... PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 Note: Overview The Atmel enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ATmega128 ...

Page 3

... GENERAL PURPOSE REGISTERS ALU STATUS REGISTER DATA REGISTER DATA DIR. PORTB REG. PORTB PORTB DRIVERS PB0 - PB7 ATmega128 PC0 - PC7 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER OSCILLATOR TIMING AND ...

Page 4

... Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications. The ATmega128 device is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...

Page 5

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega128 as listed on 73. Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... PG3 and PG4 are oscillator pins. ATmega128 6 The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. ...

Page 7

... By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Pro- gramming mode. PEN has no function during normal operation. 2467VS–AVR–02/11 , even if the ADC is not used. If the ADC is used, it should be connected ATmega128 Table 19 on page CC 7 ...

Page 8

... A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C ATmega128 8 1. 2467VS–AVR–02/11 ...

Page 9

... PORTG4 PORTG3 – – DDG4 DDG3 – – PING4 PING3 PORTF6 PORTF5 PORTF4 PORTF3 ATmega128 Bit 2 Bit 1 Bit 0 – – – – – – – – – – – – UCSZ11 UCSZ10 UCPOL1 UPE1 U2X1 ...

Page 10

... UCSR0B RXCIE0 $09 ($29) UBRR0L $08 ($28) ACSR ACD $07 ($27) ADMUX REFS1 $06 ($26) ADCSRA ADEN $05 ($25) ADCH $04 ($24) ADCL $03 ($23) PORTE PORTE7 $02 ($22) DDRE DDE7 ATmega128 10 Bit 6 Bit 5 Bit 4 Bit 3 DDF6 DDF5 DDF4 DDF3 – – – – SP14 SP13 SP12 SP11 SP6 ...

Page 11

... I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 2467VS–AVR–02/11 Bit 6 Bit 5 Bit 4 Bit 3 PINE6 PINE5 PINE4 PINE3 PINF6 PINF5 PINF4 PINF3 ATmega128 Bit 2 Bit 1 Bit 0 PINE2 PINE1 PINE0 PINF2 PINF1 PINF0 Page ...

Page 12

... Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared ATmega128 12 Operation Flags Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...

Page 13

... CLZ Clear Zero Flag SEI Global Interrupt Enable CLI Global Interrupt Disable SES Set Signed Test Flag CLS Clear Signed Test Flag 2467VS–AVR–02/11 ATmega128 Operation Flags then PC ← None then PC ← None Rd ← Rr None Rd+1:Rd ← Rr+1:Rr None Rd ← K None Rd ← ...

Page 14

... Set T in SREG CLT Clear T in SREG SEH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG CLH MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega128 14 Operation Flags V ← ← ← ← ← ← None (see specific descr ...

Page 15

... Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad 1.0mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 2467VS–AVR–02/11 (1) Ordering Code Package ATmega128L-8AU 64A ATmega128L-8MU 64M1 ATmega128-16AU 64A ATmega128-16MU 64M1 ATmega128L–8AN 64A (3) ATmega128L–8ANR 64A ATmega128L–8MN 64M1 (3) ATmega128L– ...

Page 16

... JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega128 16 B PIN 1 IDENTIFIER ...

Page 17

... Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 64M1, 64-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega128 C SEATING PLANE A1 A 0.08 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE SYMBOL A 0 ...

Page 18

... Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Stabilizing time needed when changing XDIV Register • ...

Page 19

... Always use OUT or SBI to set EERE in EECR. 2467VS–AVR–02/11 ; set global interrupt enable If ATmega128 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 20

... Reorganized the swapped chapters in rev U: 8-bit Timer/Counter 0, 16-bit TC1 and TC3, and 8-bit TC2 with PWM. Rev. 2467U-08/10 1. Updated dix A ATmega128/L 105°C. Rev. 2467T-07/10 1. Updated the 2. Added a link from and Clock Options” on page 3. Updated use of Technical Terminology in datasheet 4 ...

Page 21

... ATmega128L removed from 6. Added 7. Updated Pb-Plated packages are no longer offered, and the ordering information for these packages are removed. There will no longer exist separate ordering codes for commercial operation range, only industrial operation range. 8. Updated Merged errata description for rev.F to rev.M in Rev ...

Page 22

... Updated 3. Updated values for V 4. Updated 5. Updated description for the JTD bit on 6. Added a note regarding JTAGEN fuse to ATmega128 22 “Serial Peripheral Interface – SPI” on page “Analog to Digital Converter” on page 230 “Input Channel and Gain Selections” on page “Errata” on page 18 ...

Page 23

... Information” on page “Using all Locations of External Memory Smaller than 64 Kbyte” 32. “Default Clock Source” on page “External Clock” on page 42 320. (Timer/Counter0). ATmega128 318. “Programming the Flash” on page 315 125. from both SPI Serial Programming and Self 16. “Ordering Information” on page 37 ...

Page 24

... Added not regarding OCDEN Fuse below 10. Updated Programming Figures: Figure 135 on page 290 must be connected during Programming mode. how to program the fuses. 11. Added a note regarding usage of the PROG_PAGELOAD and PROG_PAGEREAD instructions on ATmega128 24 (Timer/Counter0). (Timer/Counter2). (Timer/Counter2). Table 81 on page 191 (USART). Table 102 on page 259 (Boundary-Scan) “ ...

Page 25

... Table 20 on page 320, Table 134 on page 323, and Table 136 on page 328. “Ordering Information” on page “Programming the Fuses” on page 317 ATmega128 section. “Address Match Unit” 36. “Alternate Functions of Port G” on page 54, “DC Characteristics” on page 15. “Typical Characteristics” on page and “ ...

Page 26

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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