Z8F0213PJ005SC Zilog, Z8F0213PJ005SC Datasheet - Page 118

• Manufacturer Part Number: Z8F0213PJ005SC
• Description: IC ENCORE MCU FLASH 2K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0213PJ005SC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3461

Table 67. UART Control 1 Register (U0CTL1)
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
MPMD[1]
R/W
7
0
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data
1 = Odd parity is transmitted and expected on all received data
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent
1 = Forces a break condition by setting the output of the transmitter to zero
STOP—Stop Bit Select
0 = The transmitter sends one stop bit
1 = The transmitter sends two stop bits
LBEN—Loop Back Enable
0 = Normal operation
1 = All transmitted data is looped back to the receiver
MPMD[1:0]—MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address)
01 = The UART generates an interrupt request only on received address bytes
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until an
address mismatch occurs
11 = The UART generates an interrupt request on all received data bytes for which the
most recent address byte matched the value in the Address Compare Register
MPEN—MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable MULTIPROCESSOR (9-bit) mode
1 = Enable MULTIPROCESSOR (9-bit) mode
MPBT—Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. The 9th bit
is used by the receiving device to determine if the data byte contains address or data infor-
mation.
MPEN
R/W
0
6
MPMD[0]
R/W
5
0
MPBT
R/W
0
4
F43H
DEPOL
R/W
0
3
Universal Asynchronous Receiver/Transmitter
BRGCTL
Z8 Encore! XP
R/W
0
2
Product Specification
RDAIRQ
R/W
1
0
®
F0823 Series
IREN
R/W
0
0
108