STM32F101C8T6 STMicroelectronics, STM32F101C8T6 Datasheet - Page 59
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STM32F101C8T6
Manufacturer Part Number
STM32F101C8T6
Description
MCU ARM 64KB FLASH/TIMER 48-LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Specifications of STM32F101C8T6
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
37
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
STM32F101x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
10 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
37
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 12-bit
Cpu Family
STM32
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
36MHz
Total Internal Ram Size
10KB
# I/os (max)
37
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6055
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STM32F101x8, STM32F101xB
5.3.14
Figure 27. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under the ambient temperature and V
in
Table 37.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 28. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
Table
NF(NRST)
IH(NRST)
IL(NRST)
Symbol
F(NRST)
the series resistance must be minimum
Table
hys(NRST)
R
PU
37. Otherwise the reset will not be taken into account by the device.
8.
(1)
(1)
(1)
(1)
PU
External
reset circuit
NRST pin characteristics
(see
EXT ERNAL
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) ≤ 2/3)T and if the duty cycle is (45-55%)
Table
(1)
0.1 µF
34).
Parameter
t r(I O)out
NRST
Doc ID 13586 Rev 14
(2)
(~10% order)
10%
V DD
50%
when loaded by 50pF
R PU
90%
.
(2)
Conditions
V
DD
IN
T
10%
=
supply voltage conditions summarized
Table 37
V
SS
50%
Filter
90%
t r(I O)out
STM32F10x
–0.5
Min
300
30
Internal reset
2
are derived from tests
IL(NRST)
Electrical characteristics
max level specified in
Typ
200
40
ai14132d
V
DD
Max
100
0.8
50
+0.5
ai14131
Unit
to
59/87
mV
kΩ
ns
ns
V