STM32F103VBT6 STMicroelectronics, STM32F103VBT6 Datasheet

MCU ARM 128KB FLASH MEM 100-LQFP

STM32F103VBT6

Manufacturer Part Number
STM32F103VBT6
Description
MCU ARM 128KB FLASH MEM 100-LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103VBT6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
20 KB
Interface Type
CAN/I2C/SPI/USART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ST-LINK
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (16-ch x 12-bit)
Controller Family/series
(ARM Cortex) STM32
No. Of I/o's
80
Ram Memory Size
20KB
Cpu Speed
72MHz
No. Of Timers
4
Cpu Family
STM32
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
72MHz
Total Internal Ram Size
20KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
For Use With
497-10048 - BOARD EVAL ACCELEROMETER497-10030 - STARTER KIT FOR STM32497-9091 - LED BOARD FOR STM32 STP16DP05497-8853 - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL - KIT IAR KICKSTART STM32 CORTEXM3497-8512 - KIT STARTER FOR STM32F10XE MCU497-8511 - KIT STARTER FOR STM32 512K FLASH497-8505 - KIT STARTER FOR STM32F10XE MCU497-8304 - KIT STM32 MOTOR DRIVER BLDC497-6438 - BOARD EVALUTION FOR STM32 512K497-6289 - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U - BOARD EVAL MCBSTM32 + ULINK2MCBSTM32 - BOARD EVAL FOR STM STM32X SER497-6053 - KIT STARTER FOR STM32497-6052 - KIT STARTER FOR STM32497-6050 - KIT STARTER FOR STM32497-6049 - KIT EVALUATION LOW COST STM32497-6048 - BOARD EVALUATION FOR STM32497-6047 - KIT DEVELOPMENT FOR STM32497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6070

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F103VBT6
Manufacturer:
STMicroelectronics
Quantity:
8 800
Part Number:
STM32F103VBT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM32F103VBT6
Manufacturer:
ST
0
Part Number:
STM32F103VBT6
Manufacturer:
ST
Quantity:
200
Part Number:
STM32F103VBT6
Manufacturer:
ST
Quantity:
6 255
Part Number:
STM32F103VBT6 .
Manufacturer:
ST
0
Part Number:
STM32F103VBT6 128 20
Manufacturer:
ST
0
Part Number:
STM32F103VBT6 LQFP100
Manufacturer:
ST
0
128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
Features
June 2010
Core: ARM 32-bit Cortex™-M3 CPU
– 72 MHz maximum frequency,
– Single-cycle multiplication and hardware
Memories
– 64 or 128 Kbytes of Flash memory
– 20 Kbytes of SRAM
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– V
2 x 12-bit, 1 µs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Temperature sensor
DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
Up to 80 fast I/O ports
– 26/37/51/80 I/Os, all mappable on 16
Medium-density performance line ARM-based 32-bit MCU with 64 or
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
division
detector (PVD)
I
external interrupt vectors and almost all
5 V-tolerant
2
BAT
Cs and USARTs
supply for RTC and backup registers
Doc ID 13587 Rev 12
Table 1.
STM32F103x8
STM32F103xB
VFQFPN48 7 × 7 mm
VFQFPN36 6 × 6 mm
Reference
Debug mode
– Serial wire debug (SWD) & JTAG interfaces
7 timers
– Three 16-bit timers, each with up to 4
– 16-bit, motor control PWM timer with dead-
– 2 watchdog timers (Independent and
– SysTick timer: a 24-bit downcounter
Up to 9 communication interfaces
– Up to 2 x I
– Up to 3 USARTs (ISO 7816 interface, LIN,
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full-speed interface
CRC calculation unit, 96-bit unique ID
Packages are ECOPACK
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
time generation and emergency stop
Window)
IrDA capability, modem control)
Device summary
STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103RB STM32F103VB,
STM32F103CB, STM32F103TB
BGA100 10 × 10 mm
2
BGA64 5 × 5 mm
C interfaces (SMBus/PMBus)
STM32F103xB
STM32F103x8
Part number
®
LQFP100 14 × 14 m
LQFP64 10 × 10 m
LQFP48 7 × 7 m
www.st.com
1/96
1

Related parts for STM32F103VBT6

STM32F103VBT6 Summary of contents

Page 1

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 ...

Page 2

Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

STM32F103x8, STM32F103xB 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Contents 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

STM32F103x8, STM32F103xB List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

List of tables Table 45. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 7

STM32F103x8, STM32F103xB List of figures Figure 1. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

List of figures Figure 43. Recommended footprint (dimensions in mm) Figure 44. LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . ...

Page 9

... This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the The medium-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual ...

Page 10

Description 2.1 Device overview Table 2. STM32F103xx medium-density device features and peripheral counts Peripheral Flash - Kbytes SRAM - Kbytes General-purpose Advanced-control SPI USART USB CAN GPIOs 12-bit synchronized ADC Number of channels CPU frequency Operating voltage ...

Page 11

STM32F103x8, STM32F103xB Figure 1. STM32F103xx performance line block diagram TRACECLK TRACED[0: NJTRST TRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF NRST VDDA VSSA 80AF PA[ 15:0] PB[ 15:0] PC[15:0] PD[15:0] PE[15:0] 4 Chann els 3 co mpl. Chann els ...

Page 12

Description Figure 2. Clock tree OSC_OUT 4-16 MHz OSC_IN OSC32_IN 32.768 kHz OSC32_OUT Main Clock Output MCO 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. ...

Page 13

STM32F103x8, STM32F103xB 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB ...

Page 14

Description 2.3 Overview ® 2.3.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs ...

Page 15

STM32F103x8, STM32F103xB This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured ...

Page 16

Description in reset mode when V external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the V /V power supply and compares it to the V DD DDA generated when V than the V threshold. ...

Page 17

STM32F103x8, STM32F103xB 2.3.13 DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each ...

Page 18

Description Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 ...

Page 19

STM32F103x8, STM32F103xB SysTick timer This timer is dedicated for OS, but could also be used as a standard downcounter. It features: ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ● Programmable ...

Page 20

Description 2.3.21 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down peripheral alternate function. Most of the GPIO pins are shared ...

Page 21

STM32F103x8, STM32F103xB 3 Pinouts and pin description Figure 3. STM32F103xx performance line LFBGA100 ballout 1 2 PC14- PC13- A PE2 OSC32_IN TAMPER-RTC PC15 BAT PE3 OSC32_OUT C OSC_IN V SS_5 PE4 D OSC_OUT V DD_5 PE5 E NRST ...

Page 22

Pinouts and pin description Figure 4. STM32F103xx performance line LQFP100 pinout VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST VSSA VREF- VREF+ VDDA PA0-WKUP 22/96 PE2 1 PE3 2 PE4 3 PE5 4 PE6 ...

Page 23

STM32F103x8, STM32F103xB Figure 5. STM32F103xx performance line LQFP64 pinout PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VBAT PD0 OSC_IN 5 PD1 OSC_OUT 6 NRST ...

Page 24

Pinouts and pin description Figure 6. STM32F103xx performance line TFBGA64 ballout 1 PC14- A OSC32_IN PC15- B OSC32_OUT C OSC_IN D OSC_OUT E NRST V SSA F V REF DDA 24/ PC13- PB9 PB4 ...

Page 25

STM32F103x8, STM32F103xB Figure 7. STM32F103xx performance line LQFP48 pinout PC13-TAMPER-RTC PC15-OSC32_OUT Figure 8. STM32F103xx performance line VFQFPN48 pinout PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD1-OSC_OUT VBAT 1 2 PC14-OSC32_IN 3 4 ...

Page 26

Pinouts and pin description Figure 9. STM32F103xx performance line VFQFPN36 pinout V OSC_IN/PD0 OSC_OUT/PD1 NRST PA0-WKUP 26/ DD_3 QFN36 V 5 SSA V 6 DDA 7 PA1 8 PA2 9 10 ...

Page 27

STM32F103x8, STM32F103xB Table 5. Medium-density STM32F103xx pin definitions Pins ...

Page 28

Pinouts and pin description Table 5. Medium-density STM32F103xx pin definitions (continued) Pins ...

Page 29

STM32F103x8, STM32F103xB Table 5. Medium-density STM32F103xx pin definitions (continued) Pins ...

Page 30

Pinouts and pin description Table 5. Medium-density STM32F103xx pin definitions (continued) Pins D10 C10 B10 A10 ...

Page 31

... This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins ...

Page 32

Memory mapping 4 Memory mapping The memory map is shown in Figure 10. Memory map 0xFFFF FFFF 7 0xE010 0000 Cortex- M3 Internal Peripherals 0xE000 0000 6 0xC000 0000 5 0xA000 0000 4 0x8000 0000 3 0x6000 0000 2 Peripherals ...

Page 33

STM32F103x8, STM32F103xB 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...

Page 34

Electrical characteristics Figure 11. Pin loading conditions 5.1.6 Power supply scheme Figure 13. Power supply scheme 5 × 100 × 4.7 µ µ µF Caution: ...

Page 35

STM32F103x8, STM32F103xB 5.1.7 Current consumption measurement Figure 14. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Current characteristics, and damage to the device. These are stress ratings only and functional ...

Page 36

Electrical characteristics Table 7. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...

Page 37

STM32F103x8, STM32F103xB Table 9. General operating conditions (continued) Symbol Power dissipation for suffix suffix 7 Ambient temperature for 6 suffix version T A Ambient temperature for 7 suffix version T Junction temperature range ...

Page 38

Electrical characteristics Table 11. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis PVDhyst Power on/power down V POR/PDR reset threshold (2) V PDR hysteresis PDRhyst (2) T Reset temporization ...

Page 39

STM32F103x8, STM32F103xB 5.3.4 Embedded reference voltage The parameters given in temperature and V Table 12. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...

Page 40

Electrical characteristics Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply current Run mode 1. Based on characterization, not tested in production. 2. External clock is 8 MHz ...

Page 41

STM32F103x8, STM32F103xB Figure 15. Typical current consumption in Run mode versus frequency (at 3 code with data processing running from RAM, peripherals enabled Figure 16. Typical current consumption ...

Page 42

Electrical characteristics Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply current Sleep mode 1. based on characterization, tested in production External clock is 8 MHz ...

Page 43

STM32F103x8, STM32F103xB Table 16. Typical and maximum current consumptions in Stop and Standby modes Symbol Parameter Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Supply current in Stop mode Regulator in ...

Page 44

Electrical characteristics Figure 18. Typical current consumption in Stop mode with regulator in Run mode versus temperature at V 300 250 200 150 100 50 0 -45 Figure 19. Typical current consumption in Stop mode with regulator in Low-power mode ...

Page 45

STM32F103x8, STM32F103xB Figure 20. Typical current consumption in Standby mode versus temperature 3.3 V and 3 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 –45 °C Typical current consumption The MCU is placed ...

Page 46

Electrical characteristics Table 17. Typical current consumption in Run mode, code with data processing running from Flash Symbol Parameter Supply I current in DD Run mode 1. Typical values are measures Add an additional power consumption of ...

Page 47

STM32F103x8, STM32F103xB Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Supply I current in DD Sleep mode 1. Typical values are measures Add an additional power consumption of 0.8 ...

Page 48

Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● all I/O pins are in input mode with a static value at V ● all peripherals are disabled unless ...

Page 49

STM32F103x8, STM32F103xB 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 20. High-speed external user clock ...

Page 50

Electrical characteristics Figure 21. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) EXTER NAL CLOCK SOURC E Figure 22. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t ...

Page 51

STM32F103x8, STM32F103xB Table 22. HSE 4-16 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F Recommended load capacitance C versus equivalent serial resistance of the crystal (R i HSE driving current 2 g Oscillator transconductance m (4) ...

Page 52

Electrical characteristics Table 23. LSE oscillator characteristics (f Symbol R Feedback resistor F Recommended load capacitance (2) C versus equivalent serial resistance of the crystal (R I LSE driving current 2 g Oscillator Transconductance m (4) t startup time SU(LSE) ...

Page 53

STM32F103x8, STM32F103xB High-speed internal (HSI) RC oscillator Table 24. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC HSI oscillator HSI oscillator (4) t su(HSI) startup time HSI oscillator power (4) I DD(HSI) consumption 1. V ...

Page 54

Electrical characteristics Table 26. Low-power mode wakeup timings Symbol (1) t WUSLEEP (1) t WUSTOP (1) t WUSTDBY 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first ...

Page 55

STM32F103x8, STM32F103xB Table 28. Flash memory characteristics (continued) Symbol Parameter I Supply current DD V Programming voltage prog 1. Guaranteed by design, not tested in production. Table 29. Flash memory endurance and data retention Symbol Parameter N Endurance END t ...

Page 56

Electrical characteristics Table 30. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce a functional disturbance Fast transient voltage burst limits applied through 100 EFTB pins to ...

Page 57

STM32F103x8, STM32F103xB 5.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a ...

Page 58

Electrical characteristics 5.3.12 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 34. I/O static characteristics Symbol Parameter Standard I/O input low level voltage V IL (1) I/O ...

Page 59

STM32F103x8, STM32F103xB Figure 25. Standard I/O input characteristics - CMOS port Figure 26. Standard I/O input characteristics - TTL port Doc ID 13587 Rev 12 Electrical characteristics 59/96 ...

Page 60

Electrical characteristics Figure 27 tolerant I/O input characteristics - CMOS port Figure 28 tolerant I/O input characteristics - TTL port Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and ...

Page 61

STM32F103x8, STM32F103xB Output voltage levels Unless otherwise specified, the parameters given in performed under ambient temperature and V Table 9. All I/Os are CMOS and TTL compliant. Table 35. Output voltage characteristics Symbol Output low level voltage for an I/O ...

Page 62

Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 36, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 9. Table 36. I/O AC ...

Page 63

STM32F103x8, STM32F103xB Figure 29. I/O AC characteristics definition EXT ERNAL OUTPUT ON 50pF Maximum frequency is achieved 2/3)T and if the duty cycle is (45-55%) 5.3.13 NRST pin characteristics The NRST pin input ...

Page 64

Electrical characteristics Figure 30. Recommended NRST pin protection External reset circuit 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the V Table 37. ...

Page 65

STM32F103x8, STM32F103xB 5.3.15 Communications interfaces interface characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in The STM32F103xx performance line communication protocol with the following restrictions: ...

Page 66

Electrical characteristics 2 Figure 31 bus AC waveforms and measurement circuit I²C bus Start SDA t f(SDA) t h(STA) SCL t w(SCLH) 1. Measurement points are done at CMOS levels: 0.3V Table 40. SCL frequency ( ...

Page 67

STM32F103x8, STM32F103xB SPI interface characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in Refer to Section 5.3.12: I/O port characteristics function characteristics (NSS, SCK, MOSI, MISO). Table 41. SPI characteristics Symbol f ...

Page 68

Electrical characteristics Figure 32. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...

Page 69

STM32F103x8, STM32F103xB Figure 34. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V USB ...

Page 70

Electrical characteristics Table 43. USB DC electrical characteristics Symbol Input levels V USB operating voltage DD (4) V Differential input sensitivity DI (4) V Differential common mode range CM (4) V Single ended receiver threshold SE Output levels V Static ...

Page 71

STM32F103x8, STM32F103xB 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in Note recommended to perform a calibration after each power-up. Table 45. ADC characteristics Symbol Parameter V ...

Page 72

Electrical characteristics Equation 1: R AIN  R ------------------------------------------------------------- - R AIN  ADC The formula above error below 1/4 of LSB. Here (from 12-bit resolution). Table 46. R AIN T (cycles) s 1.5 7.5 ...

Page 73

STM32F103x8, STM32F103xB Table 48. ADC accuracy Symbol ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be ...

Page 74

Electrical characteristics Figure 37. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance ...

Page 75

STM32F103x8, STM32F103xB Figure 39. Power supply and reference decoupling ( and V REF+ REF– 5.3.18 Temperature sensor characteristics Table 49. TS characteristics Symbol ( (1) Avg_Slope ( (2) t START (3)(2) T S_temp 1. ...

Page 76

Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...

Page 77

STM32F103x8, STM32F103xB Figure 40. VFQFPN36 mm, 0.5 mm pitch, package outline Seating plane Pin # 0.20 1. Drawing is not to scale. ...

Page 78

Package characteristics Figure 42. VFQFPN48 mm, 0.5 mm pitch, package (1) outline Seating Plane Bottom View D2 1. Drawing is not to scale. 2. The back-side pad is not internally ...

Page 79

STM32F103x8, STM32F103xB Figure 44. LFBGA100 - low profile fine pitch ball grid array package outline 1. Drawing is not to scale. Table 52. LFBGA100 - low profile fine pitch ball grid array ...

Page 80

Package characteristics Figure 45. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 80/96 Dpad Dsm Solder paste – Non solder mask defined pads are recommended – mils screen print Dsm Doc ID 13587 Rev 12 STM32F103x8, ...

Page 81

STM32F103x8, STM32F103xB Figure 46. LQFP100 100-pin low-profile quad flat package outline 100 26 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in ...

Page 82

Package characteristics Figure 48. LQFP64 mm, 64-pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 54. LQFP64 mm, 64-pin low-profile quad ...

Page 83

STM32F103x8, STM32F103xB Figure 50. TFBGA64 - active ball array mm, 0.5 mm pitch, package outline Seating plane 1. Drawing is not to scale. Table 55. TFBGA64 - active ball array, 5 ...

Page 84

Package characteristics Figure 51. Recommended PCB design rules for pads (0.5 mm pitch BGA) Dpad Dsm 1. Non solder mask defined (NSMD) pads are recommended mils solder paste screen printing process 84/96 Pitch D pad Dsm ...

Page 85

STM32F103x8, STM32F103xB Figure 52. LQFP48 mm, 48-pin low-profile quad flat package outline Seating plane ccc Pin 1 1 identification 1. Drawing is not to scale. ...

Page 86

Package characteristics 6.2 Thermal characteristics The maximum chip junction temperature (T Table 9: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in C, ●  ...

Page 87

STM32F103x8, STM32F103xB 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to ...

Page 88

Package characteristics Using the values obtained in – For LQFP100, 46 °C 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C Jmax This is within the range of the suffix ...

Page 89

STM32F103x8, STM32F103xB 7 Ordering information scheme Table 58. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count pins pins ...

Page 90

Revision history 8 Revision history Table 59. Document revision history Date Revision 01-jun-2007 20-Jul-2007 90/96 1 Initial release. Flash memory size modified in BGA100 pins added to Table 5: Medium-density STM32F103xx pin definitions. Figure 3: STM32F103xx performance line LFBGA100 ballout ...

Page 91

STM32F103x8, STM32F103xB Table 59. Document revision history (continued) Date Revision 18-Oct-2007 STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: STM32F103xx medium-density device features and peripheral counts) VFQFPN36 package added (see All packages are ECOPACK® compliant. Package mechanical ...

Page 92

Revision history Table 59. Document revision history (continued) Date Revision 22-Nov-2007 92/96 Document status promoted from preliminary data to datasheet. The STM32F103xx is USB certified. Small text changes. Power supply schemes on page 15 communication peripherals corrected for STM32F103Tx and ...

Page 93

STM32F103x8, STM32F103xB Table 59. Document revision history (continued) Date Revision 14-Mar-2008 21-Mar-2008 22-May-2008 Figure 2: Clock tree on page 12 Maximum T value given in J page 36. CRC feature added (see unit on page 9 and Figure 10: Memory ...

Page 94

Revision history Table 59. Document revision history (continued) Date Revision 21-Jul-2008 22-Sep-2008 94/96 Power supply supervisor operating conditions. Capacitance modified in Figure 13: Power supply scheme on page Table notes revised in Section 5: Electrical Table 16: Typical and maximum ...

Page 95

STM32F103x8, STM32F103xB Table 59. Document revision history (continued) Date Revision 23-Apr-2009 22-Sep-2009 03-Jun-2010 I/O information clarified on page Figure 3: STM32F103xx performance line LFBGA100 ballout Figure 10: Memory map added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to ...

Page 96

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

Related keywords