EZ80F92AZ020SG Zilog, EZ80F92AZ020SG Datasheet - Page 109
EZ80F92AZ020SG
Manufacturer Part Number
EZ80F92AZ020SG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3872
EZ80F92AZ020SG
EZ80F92AZ020SG
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PS015313-0508
Real-Time Clock Alarm Control Register
This register contains alarm enable bits for the Real-Time Clock. The RTC_ACTRL regis-
ter is cleared by a RESET. See
Table 50. Real-Time Clock Alarm Control Register; (RTC_ACTRL = 00ECh)
Real-Time Clock Control Register
This register contains control and status bits for the Real-Time Clock. Some bits in the
RTC_CTRL register are cleared by a RESET. The ALARM flag and associated interrupt
(if INT_EN is enabled) are cleared by reading this register. The ALARM flag is updated
by clearing (locking) the RTC_UNLOCK bit or by an increment of the RTC count. Writ-
ing to the RTC_CTRL register also resets the RTC clock divider allowing the RTC to be
synchronized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP
mode. This bit can be checked after RESET to determine if a sleep-mode recovery is
caused by the RTC. SLP_WAKE is cleared by a Read of the RTC_CTRL register.
Setting BCD_EN causes the RTC to use BCD counting in all registers including the alarm
set points.
Bit
Reset
CPU Access
Note: X = Unchanged by RESET; R/W = Read/Write; R = Read Only.
Bit
Position
[7:4]
3
ADOW_EN
2
AHRS_EN
1
AMIN_EN
0
ASEC_EN
Value Description
0000
0
1
0
1
0
1
0
1
Reserved.
The day-of-the-week alarm is disabled.
The day-of-the-week alarm is enabled.
The hours alarm is disabled.
The hours alarm is enabled.
The minutes alarm is disabled.
The minutes alarm is enabled.
The seconds alarm is disabled.
The seconds alarm is enabled.
R
7
0
Table
R
6
0
50.
R
5
0
R
4
0
R/W
3
0
Product Specification
R/W
2
0
Real-Time Clock
R/W
1
0
R/W
0
0
102
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