EZ80F92AZ020SG Zilog, EZ80F92AZ020SG Datasheet - Page 174
EZ80F92AZ020SG
Manufacturer Part Number
EZ80F92AZ020SG
Description
IC ACCLAIM MCU 128KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F92AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F92x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3872
EZ80F92AZ020SG
EZ80F92AZ020SG
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Part Number
Manufacturer
Quantity
Price
Company:
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EZ80F92AZ020SG
Manufacturer:
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Quantity:
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EZ80F92AZ020SG
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PS015313-0508
ZDA
ZCL
ZDI Read Operations
ZDI Address
ZDI Block Write
The Block Write operation is initiated in the same manner as the single-byte Write opera-
tion, but instead of terminating the Write operation after the first data byte is transferred,
the ZDI master can continue to transmit additional bytes of data to the ZDI slave on the
eZ80F92 device. After the receipt of each byte of data the ZDI register address increments
by 1. If the ZDI register address reaches the end of the Write Only ZDI register address
space (
Write operations.
lsb of
ZDI Single-Byte Read
Single-byte Read operations are initiated in the same manner as single-byte Write opera-
tions, with the exception that the R/W bit of the ZDI register address is set to 1. Upon
receipt of a slave address with the R/W bit set to 1, the eZ80F92 device’s ZDI block loads
the selected data into the shifter at the beginning of the first cycle following the single-bit
data separator. The msb is shifted out first.
byte Read operations.
A0
7
30h
Write
8
Byte Separator
), the address stops incrementing.
Single-Bit
0/1
9
Figure 43.ZDI Block Data Write Timing
of DATA
Byte 1
msb
D7
1
D6
2
D5
3
ZDI Data Bytes
D1
7
Figure 44
Figure 43
of DATA
Byte 1
D0
lsb
8
Byte Separator
Single-Bit
displays the timing for ZDI single-
displays the timing for ZDI Block
0/1
9
D7
1
Product Specification
of DATA
Byte 2
eZ80F92/eZ80F93
msb
D6
Zilog Debug Interface
2
1
9
167
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