Z16F3211AL20SG Zilog, Z16F3211AL20SG Datasheet - Page 266

• Manufacturer Part Number: Z16F3211AL20SG
• Description: IC ZNEO MCU FLASH 32K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F3211AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F3x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 2 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4568

Table 126. Sample Time (ADCST)
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position
[7:5]
[4:0]
SST
Bit Position
[7:6]
[5:0]
SHT
Sample Time Register
00H - 3FH
7
Value (H) Description
00H -1FH
Value (H) Description
The sample time register is used to program the length of active time for the sample once a
conversion has begun by setting the
the PWM. The number of system clock cycles required for sample time varies from
system to system depending on the clock period used. You must program this register to
contain the number of system clocks required to meet a 1 s minimum sample time.
Reserved
0H
0H
R
0
Reserved—Must be 0.
Sample Hold Time
Sample Hold time in number of system clock periods to meet 1 s minimum.
Reserved—Must be 0.
Sample Settling Time
Sample settling time in num ber of system clock periods to meet 0.5 s
minimum.
6
5
1
P R E L I M I N A R Y
4
1
START
FF-E505H
bit in the ADC control register or initiated by
3
1
R/W
ST
2
1
Product Specification
ZNEO
1
1
Analog Functions
Z16F Series
0
1
250