Z16F2810FI20SG Zilog, Z16F2810FI20SG Datasheet - Page 191
Z16F2810FI20SG
Manufacturer Part Number
Z16F2810FI20SG
Description
IC ZNEO MCU FLASH 128K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2810FI20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4567
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F2810FI20SG
Manufacturer:
Zilog
Quantity:
211
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Enhanced Serial Peripheral Interface
Architecture
PS022008-0810
The Enhanced Serial Peripheral Interface (ESPI) supports SPI (Serial Peripheral Interface)
and Inter IC Sound (I
The features of the ESPI include:
•
•
•
•
•
•
•
The ESPI is a full-duplex, synchronous, character-oriented channel that supporting a
four-wire interface (serial clock, transmit and receive data, and Slave select). The ESPI
block consists of a shift register, transmit and receive data buffer registers, a baud rate
(clock) generator, control/status registers, and a control state machine. Transmit and
receive transfers are in sync as there is a single shift register for both transmit and receive
data.
Full-duplex, synchronous, character-oriented communication.
Four-wire interface (SS, SCK, MOSI, MISO).
Transmit and receive buffer registers to enable high throughput.
Transfer rates up to maximum of one-fourth the system clock frequency. This is in
SLAVE mode.
Error detection.
Dedicated programmable baud rate generator (BRG).
Data transfer control through polling, interrupt, or DMA.
Figure 34
on page 176 displays a block diagram of the ESPI.
2
S) modes of operation.
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface
Product Specification
ZNEO
Z16F Series
175
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