Z16F2810FI20SG Zilog, Z16F2810FI20SG Datasheet - Page 348
![IC ZNEO MCU FLASH 128K 80QFP](/photos/6/76/67663/269-80-qfp_sml.jpg)
Z16F2810FI20SG
Manufacturer Part Number
Z16F2810FI20SG
Description
IC ZNEO MCU FLASH 128K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2810FI20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4567
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F2810FI20SG
Manufacturer:
Zilog
Quantity:
211
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- Download datasheet (22Mb)
PS022008-0810
Clock Selection Following System Reset
Clock Failure Detection and Recovery
Unintentional access to the Oscillator Control register (OSCCTL) stops the chip by
switching to a non-functioning oscillator. Accidental alteration of the OSCCTL register is
prevented by a locking/unlocking scheme. To write the register, unlock it by making two
writes to the OSCCTL register with the values
OSCCTL register then changes the value of the register and returns the register to a locked
state. Any other sequence of oscillator control register writes has no effect. The values
written to unlock the register must be ordered correctly, but need not be consecutive. It is
possible to access other registers within the locking/unlocking operation.
The internal precision oscillator is selected following a System Reset. Startup code after
the System Reset changes the system clock source by unlocking and configuring the
OSCCTL register. If the
Low Power mode is enabled during reset. When Flash Low Power mode is enabled during
reset, the
field of the OSCDIV register will be set to
Primary Oscillator Failure
The ZNEO Z16F Series generates a System Exception when a failure of the primary
oscillator occurs if the
function in this situation, the clock failure recovery circuitry automatically forces the
Watchdog Timer oscillator to drive the system clock. Although this oscillator runs at a
much lower frequency than the original system clock, the CPU continues to operate,
allowing execution of a clock failure vector and software routines that either remedy the
oscillator failure or issue a failure alert. This automatic switch-over is not available if the
WDT is the primary oscillator.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1 kHz ±50%. For operating frequencies below 2 kHz, do not enable the clock
failure circuitry (
Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a System Exception is used if the
WDFEN
switch-over, but alerts the CPU of the failure. After a WDT failure, it is no longer possible
to detect a primary oscillator failure.
The Watchdog Timer oscillator failure detection circuit counts system clocks while
looking for a WDT clock. The logic counts 8000 system clock cycles before determining
that a failure occurred. The system clock rate determines the speed at which the WDT
failure is detected. A very slow system clock results in very slow detection times.
bit of the OSCCTL register is set. This event does not trigger an attendant clock
FLPEN
bit in the
POFEN
POFEN
must be deserted in the OSCCTL register).
LPOPT
Oscillator Control Register (OSCCTL)
P R E L I M I N A R Y
bit is set in the OSCCTL register. To maintain system
bit in
Program Memory Address 0003H
08H
E7H
.
followed by
Product Specification
18H
will be set and the
ZNEO
. A third write to the
Oscillator Control
is zero, Flash
Z16F Series
DIV
332
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