STM32F103VBH6 STMicroelectronics, STM32F103VBH6 Datasheet - Page 9

MCU ARM 128KB FLASH MEM 100-LFBG

STM32F103VBH6

Manufacturer Part Number
STM32F103VBH6
Description
MCU ARM 128KB FLASH MEM 100-LFBG
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F103VBH6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
80
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Processor Series
STM32F103x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
20 KB
Interface Type
CAN, I2C, SPI, USART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
100
Number Of Timers
3 x 16 bit
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ST-LINK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit x 2, 16 Channel
For Use With
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Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-6069

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STM32F103xx
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is
monitored for failure. During such a scenario, it is disabled and software interrupt
management follows. Similarly, full interrupt management of the PLL clock entry is available
when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the High Speed APB domains is 72 MHz. The maximum allowed frequency of the Low
Speed APB domain is 36 MHz.
Boot modes
At startup, boot pins are used to select one of three boot options:
G
G
G
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using the USART.
Power supply schemes
G
G
G
Power supply supervisor
The device has an integrated Power On Reset (POR)/Power Down Reset (PDR) circuitry. It
is always active, and ensures proper operation starting from/down to 2 V. The device
remains in reset mode when V
for an external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
when V
interrupt service routine can then generate a warning message and/or put the MCU into a
safe state. The PVD is enabled by software.
Refer to
V
DD
POR/PDR
Boot from User Flash
Boot from System Memory
Boot from SRAM
V
Provided externally through V
V
and PLL. In V
V
registers (through power switch) when V
power supply and compares it to the V
DD
SSA
BAT
DD
Table 9: Embedded reset and power control block characteristics
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
and V
drops below the V
DDA
PVD
= 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
DD
.
range (ADC is limited at 2.4 V).
PVD
DD
is below a specified threshold, V
and/or when V
DD
pins.
PVD
DD
threshold. An interrupt can be generated
DD
is not present.
is higher than the V
POR/PDR
PVD
, without the need
for the values of
threshold. The
Description
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