C8051F813-GM Silicon Laboratories Inc, C8051F813-GM Datasheet - Page 128
C8051F813-GM
Manufacturer Part Number
C8051F813-GM
Description
IC MCU 8BIT 8KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F81xr
Datasheet
1.C8051F800DK.pdf
(250 pages)
Specifications of C8051F813-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051F8x
Core
8051
Data Bus Width
16 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F800DK
Minimum Operating Temperature
- 55 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1786-5
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C8051F80x-83x
SFR Definition 21.2. RSTSRC: Reset Source
SFR Address = 0xEF
128
Note: Do not use read-modify-write operations on this register
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
FERROR Flash Error Reset Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
MCDRSF Missing Clock Detector
C0RSEF Comparator0 Reset Enable
SWRSF
PINRSF
Unused
PORSF
Name
R
7
0
Unused.
and Flag.
Software Reset Force and
Flag.
Enable and Flag.
Power-On / V
Reset Flag, and V
Reset Enable.
HW Pin Reset Flag.
FERROR
Varies
R
6
Description
DD
C0RSEF
Varies
Monitor
R/W
DD
5
monitor
SWRSF
Varies
R/W
Rev. 1.0
4
Don’t care.
N/A
Writing a 1 enables
Comparator0 as a reset
source (active-low).
Writing a 1 forces a sys-
tem reset.
Writing a 1 enables the
Missing Clock Detector.
The MCD triggers a reset
if a missing clock condition
is detected.
Writing a 1 enables the
V
source.
Writing 1 to this bit
before the V
is enabled and stabilized
may cause a system
reset.
N/A
DD
monitor as a reset
WDTRSF
Varies
Write
R
3
DD
monitor
MCDRSF
Varies
R/W
2
0
Set to 1 if Flash
read/write/erase error
caused the last reset.
Set to 1 if Comparator0
caused the last reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Set to 1 if Watchdog Timer
overflow caused the last
reset.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
Set to 1 anytime a power-
on or V
occurs.
When set to 1 all other
RSTSRC flags are inde-
terminate.
Set to 1 if RST pin caused
the last reset.
PORSF
Varies
R/W
DD
1
Read
monitor reset
PINRSF
Varies
R
0
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