C8051F813-GM Silicon Laboratories Inc, C8051F813-GM Datasheet - Page 154
C8051F813-GM
Manufacturer Part Number
C8051F813-GM
Description
IC MCU 8BIT 8KB FLASH 20QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F81xr
Datasheet
1.C8051F800DK.pdf
(250 pages)
Specifications of C8051F813-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051F8x
Core
8051
Data Bus Width
16 bit
Data Ram Size
512 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F800DK
Minimum Operating Temperature
- 55 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1786-5
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C8051F80x-83x
SFR Definition 23.8. P0MDIN: Port 0 Input Mode
SFR Address = 0xF1
SFR Definition 23.9. P0MDOUT: Port 0 Output Mode
SFR Address = 0xA4
154
Name
Reset
Name
Reset
7:0
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
Bit
Bit
Type
Type
Bit
Bit
P0MDIN[7:0]
Name
Name
7
1
7
0
Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled. In order for the P0.n pin to be in analog mode, there
MUST be a ‘1’ in the Port Latch register corresponding to that pin.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
These bits are ignored if the corresponding bit in register P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
6
1
6
0
5
1
5
0
Rev. 1.0
P0MDOUT[7:0]
4
1
4
0
P0MDIN[7:0]
R/W
R/W
Function
Function
3
1
3
0
2
1
2
0
1
1
1
0
0
1
0
0
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