C8051F715-GQ Silicon Laboratories Inc, C8051F715-GQ Datasheet - Page 224
![IC 8051 MCU 8K FLASH 48-TQFP](/photos/12/16/121648/c8051f715-gq_sml.jpg)
C8051F715-GQ
Manufacturer Part Number
C8051F715-GQ
Description
IC 8051 MCU 8K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F71xr
Specifications of C8051F715-GQ
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1619
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F715-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F715-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F70x/71x
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “30.3.4. SCL Low Timeout” on page 221). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 30.4).
224
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
EXTHOLD
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
0
1
Table 30.2. Minimum SDA Setup and Hold Times
Minimum SDA Setup Time
1 system clock + s/w delay
T
low
11 system clocks
– 4 system clocks
or
Rev. 1.0
*
Minimum SDA Hold Time
12 system clocks
3 system clocks
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