C8051F715-GQ Silicon Laboratories Inc, C8051F715-GQ Datasheet - Page 280
![IC 8051 MCU 8K FLASH 48-TQFP](/photos/12/16/121648/c8051f715-gq_sml.jpg)
C8051F715-GQ
Manufacturer Part Number
C8051F715-GQ
Description
IC 8051 MCU 8K FLASH 48-TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F71xr
Specifications of C8051F715-GQ
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1635 - DEV KIT FOR C8051F700
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1619
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F715-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F715-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F70x/71x
33.3.3. Comparator 0 Capture Mode
The capture mode in Timer 3 allows Comparator 0 rising edges to be captured with the timer clocking from
the system clock or the system clock divided by 12. Timer 3 capture mode is enabled by setting TF3CEN
to 1 and T3SPLIT to 0.
When capture mode is enabled, a capture event will be generated on every Comparator 0 rising edge.
When the capture event occurs, the contents of Timer 3 (TMR3H:TMR3L) are loaded into the Timer 3
reload registers (TMR3RLH:TMR3RLL) and the TF3H flag is set (triggering an interrupt if Timer 3 inter-
rupts are enabled). By recording the difference between two successive timer capture values, the
Comparator 0 period can be determined with respect to the Timer 3 clock. The Timer 3 clock should be
much faster than the capture clock to achieve an accurate reading.
This mode allows software to determine the time between consecutive Comparator 0 rising edges, which
can be used for detecting changes in the capacitance of a capacitive switch, or measuring the frequency of
a low-level analog signal.
280
External Clock / 8
Comparator 0
SYSCLK / 12
SYSCLK
Output
T3XCLK
0
1
Figure 33.9. Timer 3 Capture Mode Block Diagram
T
M
H
3
M
T
3
L
0
1
CKCON
M
H
T
2
T
M
2
L
M
T
1
TF3CEN
M
T
0
S
C
A
1
TR3
S
C
A
0
Capture
Rev. 1.0
TCLK
TMR3RLL TMR3RLH
TMR3L
TMR3H
TF3CEN
T3SPLIT
TF3LEN
T3XCLK
TF3H
TF3L
TR3
Interrupt
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