C8051F312-GQ Silicon Laboratories Inc, C8051F312-GQ Datasheet - Page 182
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C8051F312-GQ
Manufacturer Part Number
C8051F312-GQ
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Specifications of C8051F312-GQ
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
29
Number Of Timers
4 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F310DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 21 Channel
No. Of I/o's
29
Ram Memory Size
1280Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
32LQFP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1445 - ADAPTER PROGRAM TOOLSTICK F310
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1255
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F312-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F312-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F310/1/2/3/4/5/6/7
182
Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.
Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
SCK
SCR7
f
R/W
Bit7
SCK
R/W
Bit7
=
=
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT
places the data into the transmit buffer and initiates a transfer when in Master Mode. A read
of SPI0DAT returns the contents of the receive buffer.
These bits determine the frequency of the SCK output when the SPI0 module is configured
for master mode operation. The SCK clock frequency is a divided version of the system
clock, and is given in the following equation, where SYSCLK is the system clock frequency
and SPI0CKR is the 8-bit value held in the SPI0CKR register.
for 0 <= SPI0CKR <= 255
200kHz
f
SCK
------------------------- -
2
2000000
SCR6
R/W
Bit6
R/W
Bit6
=
4
+
------------------------------------------------ -
2
SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate
1
SFR Definition 16.4. SPI0DAT: SPI0 Data
SPI0CKR
SCR5
SYSCLK
R/W
Bit5
R/W
Bit5
SCR4
+
R/W
Bit4
R/W
Bit4
1
Rev. 1.7
SCR3
R/W
Bit3
R/W
Bit3
SCR2
R/W
Bit2
R/W
Bit2
SCR1
R/W
Bit1
R/W
Bit1
SFR Address: 0xA3
SFR Address: 0xA2
SCR0
R/W
Bit0
R/W
Bit0
00000000
Reset Value
00000000
Reset Value