MC908JL3ECDWE Freescale Semiconductor, MC908JL3ECDWE Datasheet - Page 125

• Manufacturer Part Number: MC908JL3ECDWE
• Description: IC MCU 4K FLASH 8MHZ 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL3ECDWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 26
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

13.3.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1.
COPRS — COP Rate Select Bit
COPD — COP Disable Bit
13.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
13.5 Interrupts
The COP does not generate CPU interrupt requests.
13.6 Monitor Mode
The COP is disabled in monitor mode when V
13.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
Freescale Semiconductor
COPRS selects the COP timeout period. Reset clears COPRS.
COPD disables the COP module.
1 = COP timeout period is 8176 × 2OSCOUT cycles
0 = COP timeout period is 262,128 × 2OSCOUT cycles
1 = COP module disabled
0 = COP module enabled
Address:
Address:
Reset:
Read:
Write:
Reset:
Read:
Write:
COPRS
$001F
$FFFF
Bit 7
Bit 7
R
0
Figure 13-2. Configuration Register 1 (CONFIG1)
Figure 13-3. COP Control Register (COPCTL)
= Reserved
MC68HC908JL3E Family Data Sheet, Rev. 4
R
6
0
6
R
5
0
5
TST
Low byte of reset vector
Unaffected by reset
is present on the IRQ pin or on the RST pin.
Clear COP counter
LVID
4
0
4
R
3
3
0
SSREC
2
2
0
STOP
1
1
0
COP Control Register
COPD
Bit 0
Bit 0
0
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