C8051F507-IM Silicon Laboratories Inc, C8051F507-IM Datasheet - Page 33
C8051F507-IM
Manufacturer Part Number
C8051F507-IM
Description
IC 8051 MCU 32K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F507-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
A/d Bit Size
12 bit
A/d Channels Available
32
Height
0.83 mm
Length
5 mm
Supply Voltage (max)
5.25 V
Supply Voltage (min)
1.8 V
Width
5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1525-5
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- Download datasheet (3Mb)
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 3x3 array of 1.20 mm x 1.10 mm openings on a 1.40 mm pitch should be used for the center pad.
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Dimension
calculated based on a Fabrication Allowance of 0.05 mm.
metal pad is to be 60 m minimum, all the way around the pad.
good solder paste release.
Components.
C1
C2
X1
e
Table 4.4. QFN-48 Landing Diagram Dimensions
6.80
6.80
0.20
Min
Figure 4.4. QFN-48 Landing Diagram
0.50 BSC
Max
6.90
6.90
0.30
Rev. 1.2
Dimension
X2
Y1
Y2
C8051F50x/F51x
4.00
0.75
4.00
Min
Max
4.10
0.85
4.10
33
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