C8051F351-GM Silicon Laboratories Inc, C8051F351-GM Datasheet - Page 199
![IC 8051 MCU 8K FLASH 28MLP](/photos/6/93/69391/sl-28-mlp_sml.jpg)
C8051F351-GM
Manufacturer Part Number
C8051F351-GM
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F351-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
28-MLP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x24b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F350DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 24-bit
On-chip Dac
2-ch x 8-bit
Package
28QFN
Device Core
8051
Family Name
C8051F35x
Maximum Speed
50 MHz
Data Rom Size
128 B
Height
0.88 mm
Length
5 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1083 - DEV KIT FOR F350/351/352/353
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1271
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F351-GM
Manufacturer:
SiliconL
Quantity:
5
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
TF1
R/W
Bit7
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is auto-
matically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 1 service routine if IT1 = 1. When IT1 = 0, this flag is set to ‘1’ when /INT1 is active as
defined by bit IN1PL in register IT01CF (see SFR Definition 12.5).
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be edge or level sensitive. /INT1
is configured active low or high by the IN1PL bit in the IT01CF register (see SFR Definition
12.5).
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be
cleared by software but is automatically cleared when the CPU vectors to the External Inter-
rupt 0 service routine if IT0 = 1. When IT0 = 0, this flag is set to ‘1’ when /INT0 is active as
defined by bit IN0PL in register IT01CF (see SFR Definition 12.5).
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be edge or level sensitive. /INT0
is configured active low or high by the IN0PL bit in register IT01CF (see SFR Definition
12.5).
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
TR1
R/W
Bit6
SFR Definition 22.1. TCON: Timer Contro
TF0
R/W
Bit5
TR0
R/W
Bit4
Rev. 1.1
R/W
IE1
Bit3
R/W
IT1
Bit2
C8051F350/1/2/3
R/W
IE0
Bit1
SFR Address:
R/W
IT0
Bit0
0x88
00000000
Addressable
Reset Value
Bit
199