C8051F366-GQ Silicon Laboratories Inc, C8051F366-GQ Datasheet - Page 104

• Manufacturer Part Number: C8051F366-GQ
• Description: IC 8051 MCU 32K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F366-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1648

C8051F360/1/2/3/4/5/6/7/8/9
9.5.
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is
halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is
stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock
frequency and the number of peripherals left in active mode before entering Idle. Stop mode consumes the
least power. SFR Definition 9.11 describes the Power Control Register (PCON) used to control the CIP-
51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and put into low power mode. Digital
peripherals, such as timers or serial buses, draw little power whenever they are not in use. Turning off the
Flash memory saves power, similar to entering Idle mode. Turning off the oscillator saves even more
power, but requires a reset to restart the MCU.
The C8051F36x devices feature an additional low-power SUSPEND mode, which stops the internal oscil-
lator until an awakening event occurs. See Section “16.1.1. Internal Oscillator Suspend Mode” on
page 170 for more information.
104
Bits 7–0: ACC: Accumulator.
Bits 7–0: B: B Register.
SFR Page:
SFR Address:
SFR Page:
SFR Address:
ACC.7
R/W
R/W
B.7
Bit7
Bit7
Power Management Modes
This register is the accumulator for arithmetic operations.
This register serves as a second accumulator for certain arithmetic operations.
all pages
0xE0
all pages
0xF0
ACC.6
R/W
R/W
B.6
Bit6
Bit6
ACC.5
SFR Definition 9.9. ACC: Accumulator
R/W
R/W
B.5
Bit5
Bit5
(bit addressable)
(bit addressable)
SFR Definition 9.10. B: B Register
ACC.4
R/W
R/W
B.4
Bit4
Bit4
Rev. 1.0
ACC.3
R/W
R/W
B.3
Bit3
Bit3
ACC.2
R/W
R/W
Bit2
B.2
Bit2
ACC.1
R/W
R/W
B.1
Bit1
Bit1
ACC.0
R/W
R/W
B.0
Bit0
Bit0
00000000
00000000
Reset Value
Reset Value