C8051F412-GQ Silicon Laboratories Inc, C8051F412-GQ Datasheet - Page 188

• Manufacturer Part Number: C8051F412-GQ
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F41xr

Specifications of C8051F412-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 20x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 24
• Ram Memory Size: 2368Byte
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1453 - ADAPTER PROGRAM TOOLSTICK F410336-1317 - KIT EVAL FOR C8051F411336-1314 - KIT DEV FOR C8051F41X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1310

C8051F410/1/2/3
Reads and writes of RAMDATA load the value at address RAMADDR into RTC0DAT. The following exam-
ple writes 0xA5 to address 0x20 in the RAM and reads the value back to a temporary variable:
// in 'C':
unsigned char temp = 0x00;
// Unlock the smaRTClock interface
RTC0KEY = 0xA5;
RTC0KEY = 0xF1;
// Enable the smaRTClock
RTC0ADR = 0x06; // address the RTC0CN register
RTC0DAT = 0x80; // enable the smaRTClock
while ((RTC0ADR & 0x80) == 0x80);
// Write to the smaRTClock RAM
RTC0ADR = 0x0E;// address the RAMADDR register
RTC0DAT = 0x20;// write the address of 0x20 to RAMADDR
while ((RTC0ADR & 0x80) == 0x80);// poll on the BUSY bit
RTC0ADR = 0x0F;// address the RAMDATA register
RTC0DAT = 0xA5;// write 0xA5 to RAM address 0x20
while ((RTC0ADR & 0x80) == 0x80);
// Read from the smaRTClock RAM
RTC0ADR = 0x0E;// address the RAMADDR register
RTC0DAT = 0x20;// write the address of 0x20 to RAMADDR
while ((RTC0ADR & 0x80) == 0x80);
RTC0ADR = 0x0F;
RTC0ADR |= 0x80; // initiate a read of the RAMDATA register
while ((RTC0ADR & 0x80) == 0x80);
temp = RTC0DAT; // read the value of RAM address 0x20
; in assembly:
188
Bit 7:
Internal Register Definition 20.9. RAMDATA: smaRTClock Backup RAM Data
; Unlock the smaRTClock interface
mov RTC0KEY, #0A5h
mov RTC0KEY, #0F1h
R/W
Bit7
Note: This register is not an SFR. It can only be accessed indirectly through RTC0ADR and RTC0DAT.
RAMDATA: smaRTClock Battery Backup RAM Data Bits.
These bits provide read and write access to the smaRTClock Backup RAM byte that is
selected by RAMADDR.
R/W
Bit6
// address the RAMDATA register
R/W
Bit5
R/W
Bit4
// poll on the BUSY bit
// poll on the BUSY bit
// poll on the BUSY bit
// poll on the BUSY bit
Rev. 1.1
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
smaRTClock
00000000
Reset Value
Address:
0x0F