C8051F412-GQ Silicon Laboratories Inc, C8051F412-GQ Datasheet - Page 97

• Manufacturer Part Number: C8051F412-GQ
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F41xr

Specifications of C8051F412-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 20x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F4x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F410DK
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 24
• Ram Memory Size: 2368Byte
• Cpu Speed: 50MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F41x
• Maximum Speed: 50 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1453 - ADAPTER PROGRAM TOOLSTICK F410336-1317 - KIT EVAL FOR C8051F411336-1314 - KIT DEV FOR C8051F41X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1310

POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Notes:
1. Assumes PFEN = 1 for all instruction timing.
2. MOVC instructions take 4 to 7 clock cycles depending on instruction alignment and the FLRT setting (SFR
Definition 16.3. FLSCL: Flash Scale).
Mnemonic
Table 10.1. CIP-51 Instruction Set Summary
Pop direct byte from stack
Exchange Register with A
Exchange direct byte with A
Exchange indirect RAM with A
Exchange low nibble of indirect RAM with A
Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not equal
Compare immediate to indirect and jump if not equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Boolean Manipulation
Program Branching
Rev. 1.1
Description
C8051F410/1/2/3
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