R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 270

IC R8C MCU FLASH 32LQFP

R5F21134DFP#U0

Manufacturer Part Number
R5F21134DFP#U0
Description
IC R8C MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/13r
Datasheets

Specifications of R5F21134DFP#U0

Core Size
16-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
R8C
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
No. Of I/o's
22
Eeprom Memory Size
4KB
Ram Memory Size
1024Byte
Cpu Speed
20MHz
No. Of Timers
16
Digital Ic Case
RoHS Compliant
Controller Family/series
R8C/13
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21134DFP#U0R5F21134DFP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
R5F21134DFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev.2.00 Oct 17, 2005
REJ09B0001-0200
Table 5.2.1 Interrupt Priority Levels
Chapter 5
5.2.3 ILVL2 to ILVL0 bis, IPL
ILVL2–ILVL0
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in
relation to IPL.
The following lists the conditions under which an interrupt request is acknowledged:
• I flag
• IR bit
• Interrupt priority level
The I flag, bits ILVL2 to ILVL0, and IPL are independent of each other, and they do not affect each other.
When the IPL or the interrupt priority level of an interrupt is changed, the altered level is reflected in
interrupt handling with the following timing:
• If the IPL is changed by an REIT instruction, the new level takes effect beginning with the instruction
• If the IPL is changed by a POPC, LDC, or LDIPL instruction, the new level takes effect beginning with
• If the interrupt priority level of a particular interrupt is changed by an instruction such as MOV, the
new level takes effect beginning with the instruction that is executed two or three clock cycles after the
that is executed two clock cycles after the last clock cycle of the REIT instruction.
the instruction that is executed three clock cycles after the last clock cycle of the instruction used.
last clock cycle of the instruction used.
101
000
001
010
011
100
110
111
2
2
2
2
2
2
2
2
Interrupts
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
page 250 of 263
Interrupt Priority
Level
= 1
= 1
> IPL
Priority
High
Low
Table 5.2.2 Interrupt Priority Levels Enabled by IPL
010
101
110
111
000
001
011
100
IPL
2
2
2
2
2
2
2
2
Interrupt levels 5 and above are enabled.
Interrupt levels 1 and above are enabled.
Interrupt levels 2 and above are enabled.
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
Interrupt levels 6 and above are enabled.
Interrupt levels 7 and above are enabled.
All maskable interrupts are disabled.
Enabled interrupt priority
levels
5.2 Interrupt Control

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