C8051F342-GQ Silicon Laboratories Inc, C8051F342-GQ Datasheet - Page 293

IC 8051 MCU FLASH 64K 32LQFP

C8051F342-GQ

Manufacturer Part Number
C8051F342-GQ
Description
IC 8051 MCU FLASH 64K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheets

Specifications of C8051F342-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
5.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
17-ch x 10-bit
No. Of I/o's
25
Ram Memory Size
4352Byte
Cpu Speed
48MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X336-1482 - DAUGHTER CARD TOOLSTCK C8051F342770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1300

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23.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (/RST) and C2D (P3.0) pins. Note that
the C2D pin is shared on the 32-pin packages only (C8051F342/3/6/7/9). In most applications, external
resistors are required to isolate C2 interface traffic from the user application. A typical isolation configura-
tion is shown in Figure 23.1.
The configuration in Figure 23.1 assumes the following:
Additional resistors may be necessary depending on the specific application.
1. The user input (b) cannot change state while the target device is halted.
2. The /RST pin on the target device is used as an input only.
/Reset (a)
Output (c)
Figure 23.1. Typical C2 Pin Sharing
Input (b)
C2 Interface Master
C8051F340/1/2/3/4/5/6/7/8/9
Rev. 1.1
C2CK
C2D
C8051Fxxx
293

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