C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 231

• Manufacturer Part Number: C8051F046-GQ
• Description: IC 8051 MCU 32K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F046-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1211

18.2. CAN Registers
CAN registers are classified as follows:
1. CAN Controller Protocol Registers: CAN control, interrupt, error control, bus status, test
2. Message Object Interface Registers: Used to configure 32 Message Objects, send and
3. Message Handler Registers: These read only registers are used to provide information to
4. CIP-51 MCU Special Function Registers (SFR): Six registers located in the CIP-51 MCU
18.2.1. CAN Controller Protocol Registers
The CAN Control Protocol Registers are used to configure the CAN controller, process interrupts, monitor
bus status, and place the controller in test modes. The CAN controller protocol registers are accessible
using CIP-51 MCU SFR’s by an indexed method, and some can be accessed directly by addressing the
SFR’s in the CIP-51 SFR map for convenience.
The registers are: CAN Control Register (CAN0CN), CAN Status Register (CAN0STA), CAN Test Register
(CAN0TST), Error Counter Register, Bit Timing Register, and the Baud Rate Prescaler (BRP) Extension
Register. CAN0STA, CAN0CN, and CAN0TST can be accessed via CIP-51 MCU SFR’s. All others are
accessed indirectly using the CAN address indexed method via CAN0ADR, CAN0DATH, and CAN0DATL.
Please refer to the Bosch CAN User’s Guide for information on the function and use of the CAN Control
Protocol Registers.
18.2.2. Message Object Interface Registers
There are two sets of Message Object Interface Registers used to configure the 32 Message Objects that
transmit and receive data to and from the CAN bus. Message objects can be configured for transmit or
receive, and are assigned arbitration message identifiers for acceptance filtering by all CAN nodes.
Message Objects are stored in Message RAM, and are accessed and configured using the Message
Object Interface Registers. These registers are accessed via the CIP-51’s CAN0ADR and CAN0DAT reg-
isters using the indirect indexed address method.
Please refer to the Bosch CAN User’s Guide for information on the function and use of the Message Object
Interface Registers.
modes.
receive data to and from Message Objects. The CIP-51 MCU accesses the CAN mes-
sage RAM via the Message Object Interface Registers. Upon writing a message object
number to an IF1 or IF2 Command Request Register, the contents of the associated
Interface Registers (IF1 or IF2) will be transferred to or from the message object in CAN
RAM.
the CIP-51 MCU about the message objects (MSGVLD flags, Transmission Request
Pending, New Data Flags) and Interrupts Pending (which Message Objects have caused
an interrupt or status interrupt condition).
memory map that allow direct access to certain CAN Controller Protocol Registers, and
Indexed indirect access to all CAN registers.
Step 4. Write the value 0x5EC0 to the [CAN0DATH:CAN0DATL] CIP-51 SFRs to set the Bit
Step 5. Perform other CAN initializations.
Timing Register using the indirect indexing method described on
232.
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
Section 18.2.5 on page
231