C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 37

• Manufacturer Part Number: C8051F046-GQ
• Description: IC 8051 MCU 32K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F046-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1211

4.
MONEN
VREFA
VREF0
VREF2
AIN0.0
DGND
AGND
XTAL1
XTAL2
Name
VREF
VREF
/RST
TMS
TDO
TCK
V
AV+
TDI
Pinout and Package Definitions
DD
F040/2/4/6 F041/3/5/7
37, 64, 90
38, 63, 89
8, 11, 14
9, 10, 13
26
27
28
12
16
17
15
18
Pin Numbers
1
2
3
4
5
24, 41, 57
25, 40, 56
3, 6
4, 5
58
59
60
61
62
17
18
19
7
8
9
Table 4.1. Pin Definitions
D Out JTAG Test Data Output with internal pullup. Data is
A Out Crystal Output. This pin is the excitation driver for a crystal
Type Description
D I/O Device Reset. Open-drain output of internal V
A I/O Bandgap Voltage Reference Output (all devices).
D In
D In
D In
A In
D In
A In
A In
A In
A In
A In
Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
Digital Ground. Must be tied to Ground.
Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
Analog Ground. Must be tied to Ground.
JTAG Test Mode Select with internal pullup.
JTAG Test Clock with internal pullup.
JTAG Test Data Input with internal pullup. TDI is latched
on the rising edge of TCK.
shifted out on TDO on the falling edge of TCK. TDO out-
put is a tri-state driver.
Is driven low when V
external source can initiate a system reset by driving this
pin low.
Crystal Input. This pin is the return for the internal oscilla-
tor circuit for a crystal or ceramic resonator. For a preci-
sion internal clock, connect a crystal or ceramic resonator
from XTAL1 to XTAL2. If overdriven by an external CMOS
clock, this becomes the system clock.
or ceramic resonator.
V
internal V
V
disabled.
In most applications, MONEN should be connected
directly to V
DAC Voltage Reference Input (C8051F041/3 only).
ADC0 (C8051F041/3/5/7) and ADC2 (C8051F041/3 only) 
Voltage Reference Input.
ADC0 Voltage Reference Input.
ADC2 Voltage Reference Input (C8051F040/2 only).
DAC Voltage Reference Input (C8051F040/2 only).
ADC0 Input Channel 0 (See ADC0 Specification for com-
plete description).
Rev. 1.5
DD
DD
Monitor Enable. When tied high, this pin enables the
is < 2.7 V. When tied low, the internal V
C8051F040/1/2/3/4/5/6/7
DD
monitor, which forces a system reset when
DD
.
DD
is < 2.7 V and MONEN is high. An
DD
DD
monitor is
monitor.
37