MC56F8122VFAE Freescale Semiconductor, MC56F8122VFAE Datasheet - Page 78

• Manufacturer Part Number: MC56F8122VFAE
• Description: IC DSP 16BIT 40MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8122VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 8 KB
• Operating Supply Voltage: - 0.3 V to + 4 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 8 KB
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.6.30.2
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new
interrupt service routine.
Note:
5.6.30.3
This read-only field shows the vector number (VAB[7:1]) used at the time the last IRQ was taken. This
field is only updated when the 56800E core jumps to a new interrupt service routine.
Note:
5.6.30.4
This bit allows all interrupts to be disabled.
5.6.30.5
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.7
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.9
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
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00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
0 = Normal operation (default)
1 = All interrupts disabled
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
Interrupt Priority Level (IPIC)—Bits 14–13
Vector Number - Vector Address Bus (VAB)—Bits 12–6
Interrupt Disable (INT_DIS)—Bit 5
Reserved—Bit 4
Reserved—Bit 3
IRQA State Pin (IRQA STATE)—Bit 2
Reserved—Bit 1
IRQA Edge Pin (IRQA Edg)—Bit 0
56F8322 Techncial Data, Rev. 16
Freescale Semiconductor
Preliminary