MC9S12GC32VFAE Freescale Semiconductor, MC9S12GC32VFAE Datasheet - Page 458
![IC MCU 16BIT 32K FLASH 48-LQFP](/photos/12/19/121900/mc9s12gc32vfae_sml.jpg)
MC9S12GC32VFAE
Manufacturer Part Number
MC9S12GC32VFAE
Description
IC MCU 16BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12GC16MFUE.pdf
(690 pages)
Specifications of MC9S12GC32VFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Processor Series
S12GC
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE, M68DKIT912C32SLK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12GC32VFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 15 Timer Module (TIM16B8CV1) Block Description
15.4.1
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
458
PACLK/65536
PACLK/256
Bus Clock
PAOVF
Prescaler
INTERRUPT
REQUEST
PR[2:1:0]
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
EDG0A
EDG1A
TCNT(hi):TCNT(lo)
PAOVF
PRESCALER
16-BIT COUNTER
PAOVI
CHANNEL2
CHANNEL 1
CHANNEL7
CHANNEL 0
PACNT(hi):PACNT(lo)
TC0
TC1
TC7
16-BIT COUNTER
EDG7A
EDG7B
EDG0B
EDG1B
INTERRUPT
PAOVI
LOGIC
PACLK/65536
PAOVF
PACLK/256
Figure 15-28. Detailed Timer Block Diagram
PACLK
CLEAR COUNTER
DETECT
DETECT
TE
DETECT
MC9S12C-Family / MC9S12GC-Family
EDGE
EDGE
EDGE
PAIF
C0F
C1F
C7F
PAI
PACLK
MUX
OM:OL1
OM:OL0
OM:O73
TOV1
TOV0
TOV7
CLK[1:0]
Rev 01.24
DIVIDE-BY-64
TOF
TOI
TEN
PEDGE
IOC0
CxF
CxI
C0F
C1F
PAE
IOC1
C7F
IOC7
INTERRUPT
LOGIC
IOC0 PIN
IOC1 PIN
IOC7 PIN
LOGIC
LOGIC
LOGIC
DETECT
EDGE
PAIF
channel 7 output
compare
TCRE
CH. 1 COMPARE
CH. 0 CAPTURE
CH. 1 CAPTURE
CH. 0COMPARE
CH. 7 COMPARE
CH.7 CAPTURE
PA INPUT
Freescale Semiconductor
Bus Clock
IOC0 PIN
IOC1 PIN
IOC7 PIN
TOF
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