MC9S12C32VFAE16 Freescale Semiconductor, MC9S12C32VFAE16 Datasheet - Page 413

• Manufacturer Part Number: MC9S12C32VFAE16
• Description: IC MCU 32K FLASH 16MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32VFAE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Chapter 14
Serial Peripheral Interface (SPIV3) Block Description
14.1
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral
devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
14.1.1
The SPIV3 includes these distinctive features:
14.1.2
The SPI functions in three modes, run, wait, and stop.
This is a high level description only, detailed descriptions of operating modes are contained in
Section 14.4, “Functional Description.”
Freescale Semiconductor
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Master mode and slave mode
Bidirectional mode
Slave select output
Mode fault error flag with CPU interrupt capability
Double-buffered data register
Serial clock with programmable polarity and phase
Control of SPI operation during wait mode
Run Mode
This is the basic mode of operation.
Wait Mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI
clock generation turned off. If the SPI is configured as a master, any transmission in progress stops,
but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Stop Mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI
is configured as a slave, reception and transmission of a byte continues, so that the slave stays
synchronized to the master.
Introduction
Features
Modes of Operation
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
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