MC9S12C32VFAE16 Freescale Semiconductor, MC9S12C32VFAE16 Datasheet - Page 90

IC MCU 32K FLASH 16MHZ 48-LQFP

MC9S12C32VFAE16

Manufacturer Part Number
MC9S12C32VFAE16
Description
IC MCU 32K FLASH 16MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r

Specifications of MC9S12C32VFAE16

Core Processor
HCS12
Core Size
16-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
For Use With
CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.3.3
Read: Anytime.
Write: Anytime.
90
Module Base + 0x0012
DDRM[5:0]
Reset
Field
5–0
W
R
Data Direction Port M — This register configures each port S pin as either input or output
If SPI or MSCAN is enabled, the SPI and MSCAN modules determines the pin directions. Please refer to the SPI
and MSCAN Block User Guides for details.
If the associated SCI or MSCAN transmit or receive channels are enabled, this register has no effect on the pins.
The pins are forced to be outputs if the SCI or MSCAN transmit channels are enabled, they are forced to be inputs
if the SCI or MSCAN receive channels are enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTM
0
7
Port M Data Direction Register (DDRM)
or PTIM registers, when changing the DDRM register.
= Unimplemented or Reserved
0
6
Figure 2-19. Port M Data Direction Register (DDRM)
Table 2-17. DDRM Field Descriptions
DDRM5
MC9S12C-Family / MC9S12GC-Family
0
5
DDRM4
Rev 01.24
0
4
Description
DDRM3
0
3
DDRM2
0
2
DDRM1
Freescale Semiconductor
0
1
DDRM0
0
0

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