M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 36
M30622SAFP#U5
Manufacturer Part Number
M30622SAFP#U5
Description
IC M16C MPU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(277 pages)
3.M30622SAFPU5.pdf
(617 pages)
4.M30622SAFPU5.pdf
(308 pages)
Specifications of M30622SAFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- QSK-62P_PLUS PDF datasheet
- M30622SAFPU5 PDF datasheet #2
- M30622SAFPU5 PDF datasheet #3
- M30622SAFPU5 PDF datasheet #4
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- Download datasheet (4Mb)
Bus Control
Table 1.9.8. Software waits and bus cycles
Note: When using the RDY signal, always set to “0”.
(8) BCLK output
(9) Software wait
ROM/RAM
External
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
0005
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
memory
Internal
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (0004
Area
SFR
area
16
register (address 000A
register (address 000A
) (Note) and bits 4 to 7 of the chip select control register (address 0008
Multiplex bus
Multiplex bus
Separate bus
Separate bus
Separate bus
Bus status
_______
16
16
) to “1”.
) to “1”.
_______
Wait bit
Invalid
0
1
0
0
1
0
1
________
Bits 4 to 7 of chip select
control register
0 (Note)
0 (Note)
Invalid
Invalid
Invalid
1
0
0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
1 BCLK cycle
2 BCLK cycles
3 BCLK cycles
16
).
M16C / 62A Group
Bus cycle
Mitsubishi microcomputers
16
) (Note).
33
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