M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 295
M30280FAHP#U5B
Manufacturer Part Number
M30280FAHP#U5B
Description
IC M16C/28 MCU FLASH 96K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Specifications of M30280FAHP#U5B
Core Size
16-Bit
Program Memory Size
96KB (96K x 8)
Core Processor
M16C/60
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Controller Family/series
M16C
No. Of I/o's
71
Ram Memory Size
8KB
Cpu Speed
20MHz
No. Of Timers
10
Digital Ic Case Style
LQFP
Embedded Interface Type
I2C, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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e
E
1
. v
NOTE:
J
6
Table 16.8 Start/Stop generation timing table
Table 16.9 S10 Register Settings and Functions
Figure 16.16 Start condition generation timing diagram
Figure 16.17 Stop condition generation timing diagram
0
M
As mentioned above, when the MST and TRX bits are set to "1", START condition or STOP condition mode
is entered by writing "1" or "0" to the BB flag in the S10 register and writing "0" to the PIN bit and 4 low-order
bits in the S10 register at the same time. Then SDA
and SDA
START/STOP conditions are generated. In order to set the MST and TRX bits to "1" without generating the
START/STOP conditions, write "1" to the 4 low-order bits simultaneously. Table 16.9 lists functions along
with the S10 register settings.
C
0
2
9
S
H
S
1
1
1. Actual time at the time of V
1 /
0 .
2 /
B
e
T
o
0
0
u t
8
d l
0
p
4
G
J
T
i t
7
a
i t
0
o r
R
m
0 -
. n
1
1
m
1 /
MM
X
u
e
2
e
3
p
0
, 1
0
is set to low-level ("L") in the STOP condition standby mode. When the S00 register is set, the
(
M
B
2
0
1
-
0
S
B
1
0
1
6
7
G
0
C
S
I
write signal
2
e
R
a t
2 /
I
write signal
C0 data shift register
P
n
2
page 275
e
0
0
0
t r
, 8
C0 data shift register
r e
N I
g
S /
t s i
t a
M
o t
o i
r e
1
p
A
n
6
0
0
1
1
0
0
S
1
L
C
C
S
e
o
f o
2 /
S
S
e
t t
n
CL
DA
e l
S
S
IIC
n i
8
d
3
A
CL
DA
t c
g
) B
t i
8
A
0
0
1
s
= 4MHz, The contents in () denote cycle numbers.
o i
5
S
B
n
t i
A
S
0
0
1
0
Setup
L
time
S
Setup
R
0
0
time
1
1
1
a t
B
5
5
3
3
n
0 .
0 .
0 .
0 .
d
MM
a
S
S
S
I
t
t
2
a r
a r
d r
C
e
e
e
s
s
s
s
t t
n
t t
n
t t
is left open in the START condition standby mode
2 (
5 (
2 (
5 (
s
C
n i
s
n i
s
n i
a t
m
m
o l
0
2
0
2
g
g
g
Hold
time
t i
t i
u t
k c
Hold
c
c
time
c
c
u
u
u
c y
c y
c y
c y
m
m
p
p
p
s
M
o
o
h t
h t
e
e r
e l
e l
e l
e l
d
d
a
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t s
16. MULTI-MASTER I
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t i
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g i
o i
t i
t c
2
6
2
6
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5 .
5 .
5 .
5 .
s -
n
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s
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p
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6
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C bus INTERFACE
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