M30280FAHP#U5B Renesas Electronics America, M30280FAHP#U5B Datasheet - Page 68

• Manufacturer Part Number: M30280FAHP#U5B
• Description: IC M16C/28 MCU FLASH 96K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FAHP#U5B

• Core Size: 16-Bit
• Program Memory Size: 96KB (96K x 8)
• Core Processor: M16C/60
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Controller Family/series: M16C
• No. Of I/o's: 71
• Ram Memory Size: 8KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M
R
R
e
E
1
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J
Figure 7.5 CM2 Register
6
0
C
2
9
0 .
2 /
B
0
0
8
0
Oscillation Stop Detection Register
4
G
J
NOTES:
b7
7
a
o r
10. Set the CM20 bit to “0” (disable) before setting the CM05 bit in the CM0 register.
11. The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
12. When the CM21 bit is set to “0” (on-chip oscillator turned off) and the CM05 bit is set to “1” (main clock
0 -
. n
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).
2. When the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to
3. If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock not oscillating), do not set the CM21
4. This flag is set to “1” when the main clock is detected to have stopped or when the main clock is detected
5. Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the
6. Effective when the CM07 bit in the CM0 register is set to “0”.
7. When the PM21 bit in the PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no
8. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is
9. Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back
u
b6
2
3
p
0
“1” (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the
CM21 bit is automatically set to “1” (on-chip oscillator clock) if the main clock stop is detected.
bit to “0”.
If when the CM22 bit is set to "1" an oscillation stoppage or an oscillation restart is detected, no oscillation
main clock status.
to have restarted oscillating. When this flag changes state from “0” to “1”, an oscillation stop, reoscillation
restart detection interrupt is generated. Use this flag in an interrupt routine to discriminate the causes of
interrupts between the oscillation stop, reoscillation detection interrupts and the watchdog timer interrupt.
The flag is cleared to “0” by writing a “0” by program. (Writing a “1” has no effect. Nor is it cleared to “0” by
an oscillation stop or an oscillation restart detection interrupt request acknowledged.)
stop, reoscillation restart detection interrupts are generated.
effect.
set “1” (oscillation stop, re-oscillation detection interrupt), and the CM11 bit is “1” (the CPU clock source is
PLL clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is set
to “0” under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop
detection; it is, therefore, necessary to set the CM21 bit to “1” (on-chip oscillator clock) inside the interrupt
routine.
to “1” (enable).
turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability
High).
, 1
0
0 0
b5
(
M
2
0
1
b4
0
6
7
C
b3
2 /
b2
, 8
page 48
M
b1
1
b0
6
C
f o
2 /
Bit Symbol
8
3
(b5-b4)
CM20
CM21
CM22
CM23
(b6)
CM27
) B
8
Symbol
CM2
5
Oscillation stop, re-
oscillation detection bit
(7, 9, 10, 11)
System clock select bit 2
Oscillation stop, re-
oscillation detection flag
(4)
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
X
Reserved bit
(2, 3, 6, 8, 11, 12 )
Operation select bit
(when an oscillation stop,
re-oscillation is detected)
(11)
(5)
IN
(1)
monitor flag
Bit Name
Address
000C
16
0: "Oscillation stop, re-oscillation"
1: "Oscillation stop, re-oscillation"
0: Oscillation stop detection reset
1: Oscillation stop, re-oscillation
0: Oscillation stop, re-oscillation
1: Oscillation stop, re-oscillation
0: Main clock or PLL clock
1: On-chip oscillator clock
0: Main clock oscillating
1: Main clock not oscillating
Set to “0”
not detected
detected
detection interrupt
(On-chip oscillator oscillating)
detection function enabled
detection function disabled
0X000010
After Reset
Function
2 (11)
7. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RO