M30624FGPGP#U3C Renesas Electronics America, M30624FGPGP#U3C Datasheet - Page 157
M30624FGPGP#U3C
Manufacturer Part Number
M30624FGPGP#U3C
Description
IC M16C MCU FLASH 256K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30624FGPGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 4 Instruction Code
(1) Mnemonic
(2) Syntax
(3) Instruction code
(4) Table of cycles
Shows the mnemonic explained in this page.
Shows an instruction syntax using symbols.
Shows instruction code. Entered in ( ) are omitted depending on src/dest you selected.
Contents at addresses following (start address of instruction + 2) are arranged as follows:
Shows the number of cycles required to execute this instruction and the number of instruction bytes.
There is a chance that the number of cycles increases due to an effect of software wait.
Instruction bytes are indicated on the left side of the slash and execution cycles are indicated on the right side.
Correspondence
b7
.size
.W
Content at start address
0 1 1 1 0 1 0 SIZE 1 1 0 0
.B
SIZE
0
1
of instruction
abs20
dsp20
#IMM20
dsp8
#IMM8
dsp16
abs16
#IMM16
Rn
An
[An]
b7
b7
b7
b0 b7
Low-order 8bit
Low-order 8bit
8bit
+0
Content at (start address
Correspondence
dest
R0L/R0
R0H/R1
R1L/R2
R1H/R3
A0
A1
[A0]
[A1]
of instruction+1)
b0
b0
b0
b7
b7
Middle-order 8bit
High-order 8bit
139
DEST
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
DEST
+1
Correspondence
b0
dsp:8[An]
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB]
abs16
b0
b0
b7
0 0 0 0
(
dest code
Contents at addresses following
(start address of instruction + 2)
dsp8
+2
dsp16/abs16
dest
High-order
(See the following figure.)
4bit
4.1
dsp:8[A0]
dsp:8[A1]
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
abs16
b0
Guide to This Chapter
)
#IMM8
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
DEST
#IMM16
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