MC9S12HZ128VAL Freescale Semiconductor, MC9S12HZ128VAL Datasheet - Page 132

• Manufacturer Part Number: MC9S12HZ128VAL
• Description: IC MCU 16BIT 2K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128VAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2.4
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
4.3.2.5
Read:Anytime. Write:Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
132
RDRL[7:0]
PERL[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
RDRL7
PERL7
Reduced Drive Port L
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
Pull Device Enable Port L
0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Port L Reduced Drive Register (RDRL)
Port L Pull Device Enable Register (PERL)
0
1
7
7
RDRL6
PERL6
Figure 4-14. Port L Pull Device Enable Register (PERL)
0
1
6
6
Figure 4-13. Port L Reduced Drive Register (RDRL)
Table 4-10. RDRL Field Descriptions
Table 4-11. PERL Field Descriptions
RDRL5
PERL5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
1
5
5
RDRL4
PERL4
0
1
4
4
Description
Description
RDRL3
PERL3
0
1
3
3
RDRL2
PERL2
0
1
2
2
RDRL1
PERL1
Freescale Semiconductor
0
1
1
1
RDRL0
PERL0
0
1
0
0